Siemens Aktiengesellschaft

Oread Laboratories, Inc.

Walter Engl

Klaus Schreier

Rudolf Bitzinger

Siegfried Humml

A method provides error protection in a multiprocessor central control unit of a switching system wherein a number of central processors (CP, IOC) as well as a central memory (CMY) are connected in parallel to a central bus system (B:CMY0/B:CMY1). The processors include dual highly-synchronous parallel driven processor units (PU) --apart from a possible tolerable positive timing slip--and integral error detection circuits (V), as well as an integral local memory (LMY), in the ROM-area of which test program sections are stored for testing the respective processors (CP, IOC). Upon the detection of an error by at least one of the error detection circuits (V) of a processor (for example CPx), in the respective processor (CPx), at least if the error is not immediately correctable, the error detection circuit (V in CPx) starts isolating the respective processor (CPx) from the bus system (B:CMY). The respective processor (CPx) starts the read-out of the test program sections, stored in its own local memory (LMY), for localizing and identifying the error source and/or the defect causing such errors.

Method for operating an error protected multiprocessor central control

A method and apparatus for operating a multiprocessor control computer provides that at least one part of the central processors may be connected through switches to each half of a duplicated central bus system and through switches to each half of duplicated memory banks of a common memory. With the duplication and selectable switching, the multiprocessor control computer may be normally operated while the remainder of the computer may be connected to a special computer for modification of the normal operating program. Data already in one memory bank can also be stored in another memory bank under the same address so that after the special operating time of both memory banks, the memory banks contain the same information at the same addresses. Two specific processors are provided for operating and security functions, while the remainder of the processors carry out exchange functions. One processor controls and is loaded only to a predetermined percentage of its computing capacity while the other always holds open at least that predetermined percent of computing capacity in case it must take over the control function.

Multi-processor central control unit of a telephone exchange system and

A multiprocessor central control unit a switching system with a main memory (CMY) including, aside from a tolerable timing slip, synchronously parallel operated memory block pairs (MB3a/MB3b) during normal operation. The main memory (CMY), together with the central processors (BP, CP . . . IOC . . . ), is connected to a central bus system (B:CMY0/CMY1). The data stored in parallel in the memory blocks of the memory block pairs (e.g., MB3a/MB3b) are EDC-protected. The processors have access to the memory block pairs (e.g. MB3a/MB3b). Upon the occurrence of a multiple error in an indicated second memory block (e.g., MB3b) of a memory block pair (MB3a/MB3b), the second memory block (MB3b) is isolated from the bus system (B:CMY0/B:CMY1) via an automatic memory configuration. The first memory block (MB3a) then performs the read and/or write operations alone, while from time to time the data stored in the second memory block (MB3b) are corrected by reading out of the first memory block (MB3a) and writing into the second memory block (MB3b), but during a concurrent write operation to the first memory block (MB3a) the data to be entered is also immediately written into the second memory block (MB3b) under the same address. A synchronously parallel driven configuration processor pair (SpP0/SpP1), the operation of which is EDC or parity-bit checked, is connected directly to the main memory (CMY) rather than over the central bus system for automatic memory configuration.

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Feldkirchen, Germany

Walter Engl