International Business Machines Corporation

Walter E Mlynko

Frank Daniel Egitto

Steven J Holmes

Son Van Nguyen

Robert K Leidy

Donald M Kenney

James Allan Bruce

Edward W Sengle

Daniel A Carl

Kirk David Peterson

John C Forster

K Paul Muller

Thomas George Ference

William Francis Landers

Suryadevara Vijayakumar Babu

Harbans S Sachdev

Scott Arthur MacDonald

Robin A Susko

Joseph G Hoffarth

Leo L Linehan

Allan Robert Knoll

Michael Joseph MacDonald

Mark P Murray

John F Rembetski

Francis Emmi

Kenneth D Mack

Linda K Somerville

A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.

Combined chemical mechanical polishing and reactive ion etching process

The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.

Method of photolithographically defining three regions with one mask

Polysilicon (20) in a trench (21) is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall (26) of the trench (21) closest the beam source. Specifically, when the first side wall (26) is closest the beam source and the second side wall (27) is furthest from the beam source, the polysilicon on the first side wall (26) is almost as high as the first side wall (26), while the polysilicon on the more exposed side wall (27) is considerably lower than the first side wall (26) and approximates the shadow of the first side wall (26) on the second side wall (27) relative to the beam. The polysilicon (20) in the trench (21) may be in the shape of a solid angled block approximating the shadow line from the top of side wall (26) to side wall (27); however, it is preferred that the polysilicon take the form of a conformal layer in trench (21) prior to etching such that the polysilicon ultimately has an angled 'U' shape which approximates the shadow line. Contact is made to the polysilicon (20) using strap (23) that electrically connects the side wall (26) with the polysilicon (20). Strap (23) is sized such that it does not extend to the opposite side wall (27) of trench (21), thereby avoiding short circuits. Having the polysilicon (20) approximate the shadow line of the etch permits narrowing the distance between adjacent straps (23) and (24) in an array without the risk of creating a short circuit.

Method for preparing a narrow angle defined trench in a substrate

Polysilicon in a trench is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall of the trench closest the beam source. Specifically, when the first side wall is closest to the beam source and the second side wall is furthest from the beam source, the polysilicon on the first side wall is almost as high as the first side wall, while the polysilicon on the more exposed side wall is considerably lower than the first side wall and approximates the shadow of the first side wall on the second side wall relative to the beam. The polysilicon in the trench may be in the shape of a solid angled block approximating the shadow line from the top of side wall to the shadow line on side wall however, it is preferred that the polysilicon take the form of a conformal layer in trench prior to etching such that the polysilicon ultimately has an angled 'U' shape which approximates the shadow line. Contact is made to the polysilicon using strap that electrically connects the side wall with the polysilicon. Strap is sized such that it does not extend to the opposite side wall of trench, thereby avoiding short circuits. Having the polysilicon approximate the shadow line of the etch permits narrowing the distance between adjacent straps and in an array without the risk of creating a short.

Angle defined trench conductor for a semiconductor device

A method for transferring a pattern through a photoresist layer in the fabrication of submicron semiconductor devices structures is disclosed. A photoresist is provided on a substrate and the same is imagewise exposed with a desired pattern to form exposed and unexposed patterned areas in the top surface of the photoresist. The photoresist is then baked to form cross-linked regions in the exposed pattern areas of the photoresist. Silylation is then performed to incorporate silicon into the unexposed patterned areas of the photoresist, wherein some incorporation of silicon occurs in the exposed patterned crosslinked areas of the photoresist. The patterned photoresist is subsequently etched using a high density, low pressure, anisotropic O.sub.2 plasma alone to produce residue-free images with vertical wall profiles in the photoresist. This method is particularly advantageous with RFI reactive ion etch systems.

Residue free vertical pattern transfer with top surface imaging resists

Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.

Enhanced plasma etching

A plasma etching process is disclosed wherein the substrate to be etched is first exposed to an etchant gas containing a volatile organohalide. When the etch rate is stabilized, the organohalide in the etchant gas is replaced by oxygen whereby the etch rate of the substrate is immediately increased to a substantially higher value. When the above is repeatedly done a substantially higher average etch rate is obtained.

Method of plasma etching a substrate with a gaseous organohalide compound

Contaminant is removed from the interior of the holes in the vicinity of preselected locations by etching in a gaseous plasma wherein the sheath voltage is controlled in order to direct ions of the plasma to contact the interior of the holes in the vicinity of the preselected locations.

Process for removing contaminant

Contaminant is removed from holes by etching in a gaseous plasma by first removing contaminant from the vicinity of the edges of the hole. Next, a mask is provided in the vicinity of the edges to prevent etching by contacting with a gaseous plasma which is different from the gaseous plasma employed in the first etching step. The holes are then etched in a gaseous plasma to remove contaminant from the interior of the holes in the vicinity of the center of the holes, whereby the mask protects the edges from being etched.

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Essex Junction, VT, United States of America

Walter E Mlynko