Tandem Computers Incorporated

Walter E Gibson

Cheng-Gang Kong

Philip R Manela

Eduardo Marcelo Lipiansky

Jeffrey A Sprouse

Stephen W Hamilton

Ko Yamamoto

Jeffery A Sprouse

Michael A Plum

Javad Khakbaz

Logic circuitry in the form of an integrated circuit includes a number of scannable registers located at various locations of the logic circuitry to continuously sample signal states thereat. In response to signalling from a maintenance diagnostic processor the scannable registers can be commanded to freeze their content for extraction and observation to determining the operating condition of the logic circuitry.

Real time observation serial scan test architecture

A method is provided that provides a test of an interconnect that communicates information between two digital circuits. One of the digital circuits is constructed to be 'scannable' so that it at least includes scannable registers capable of applying signals to, and sampling signals at, the interconnect. The other digital circuit has a different scan architecture such as, for example, that specified by IEEE Standard 1149.1. The method allows the interconnect between the two digital circuits, each having scan architecture that is not compatible with that of the other, to be tested.

Interconnect testing using non-compatible scan architectures

A digital system includes a number of digital subsystems interconnected by a shared bus structure that is mutually exclusively accessible for communicating data between the subsystems. The system is structured to be tested by pseudo-random scan test methodology. Each subsystem includes a counter that, during scan test periods, provides an enable signal to the bus access or driver circuitry of the associated subsystem. A scan test operation is preceded by pre-loading each counter with a predetermined state so that, initially, and throughout the test period, one and only one digital subsystem will drive the shared data bus. Each scan sequence (comprising a scan in, an execution cycle, and a scan out of the pseudo-random test strings) will result in the counters being clocked once so that a new subsystem will be enable to drive the bus the next sequence, permitting the bus access circuitry of each subsystem, and the bus itself, to be tested.

System and method for performing improved pseudo-random testing of

A digital system, comprising a plurality of integrated circuits that are designed to be scannable for pseudo-random scan testing. Testing begins and proceeds in normal binary-tree fashion, subjecting the system to a pseudo-random scan test and developing from that test a signature that is compared to a standard signature. If the comparison is unequal, portions of the system are subjected to pseudo-random scan testing, in normal binary-tree fashion, until the integrated circuit level is reached whereat a final mis-compare for the signature developed for a integrated circuit is obtained. Then, each bit position of the scan for such integrated circuit is classified according to the source of data for its primary input, and pseudo-random scan testing conducted to extract signatures for each such classified source. When a bad signature is reached, after comparing to standard signatures, the fault has been isolated to the classified source.

Fault isolation using pseudo-random scan

A scannable logic unit includes one or more storage registers that maintain copies of data communicated from the scannable unit to registers in a nonscannable unit. When the scannable unit is subjected to a scan test, the registers will contain state information respecting that transfer to the nonscannable unit. When the scannable and nonscannable units are placed in a run condition, the registers supply to the nonscannable unit state information for continuing operation.

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Walter E Gibson