Intel Corporation

Fast-chip Incorporated

Other

Alpha Modus Ventures, LLC

Walter E Croft

Alex E Henderson

John William Hayes

Linda Elaine Eaton Hayes

Alex Henderson

Vishal Sarin

Raymond M Chu

Apparatus and system that perform the method of providing a FCoE Transformer including an Ethernet Interface and a Fibre Channel Interface, receiving, at the FCoE Transformer, an FCoE Frame via a LayerEthernet Switch, converting, at the FCoE Transformer, the FCoE Frame to a Fibre Channel Frame. The FCoE Frame includes a SOF field included in an FCoE Transport Header for providing an SOF character used to start the fibre channel frame, and the SOF field in the FCoE Transport Header is for encoding the SOF field, Fibre Channel Frame. The FCoE Frame includes an EOF field included in an FCoE Transport Header for providing an EOF character used to end the fibre channel frame, and the EOF field in the FCoE Transport Header is for encoding the EOF field, Fibre Channel Frame. The method includes transporting the Fibre Channel Frame.

Transporting fibre channel over ethernet

Apparatus and system for performing the method of providing a FCoE HBA including a Virtual Fibre Channel Port and an Ethernet Interface, providing a Layer 2 Ethernet Switch, and sending an FCoE Frame via the Layer 2 Ethernet Switch. The FCoE Frame includes a SOF field included in an FCoE Transport Header for providing an SOF character used to start a Fibre Channel Frame, and the SOF field in the FCoE Transport Header is for encoding the SOF field, Fibre Channel Frame. The FCoE Frame includes an EOF field included in an FCoE Transport Header for providing an EOF character used to end the Fibre Channel Frame, and the EOF field in the FCoE Transport Header is for encoding the EOF field, Fibre Channel Frame.

Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows existing Ethernet equipment to be placed into service as SAN components without modification.

A bicycle frame attachable kneeling pad is described. The bicycle frame attachable kneeling pad is adaptable to a standard bicycle to provide new coaster usage where a user can propel forward with an active push leg, like a scooter, while resting a passive or compromised leg in the kneeling pad. The bicycle frame attachable kneeling pad includes a kneeling pad for supporting a user's passive or compromised leg while coasting on the bicycle, and a frame assembly for facilitating the assembly of the kneeling pad to the bicycle frame. The frame assembly may further include one or more crank arms that are attachable to a bottom bracket of the bicycle. The crank arms may then assemble with the frame member to ultimately attach the kneeling pad to the bicycle frame to provide the new coaster usage.

Bicycle frame attachable kneeling pad

A kneel push cycle apparatus that includes a kneeling pad disposed upon a suspension member coupled to a frame member, said frame member disposed between a directable front wheel and at least one rear wheel, wherein a user is enabled to kneel upon the kneeling pad with one leg and propel the kneel push cycle apparatus at a desired velocity by use of the other leg in striding contact with a ground surface, whereby expedient locomotion and voluble travel is enabled for a user desirous to maintain at least one lower leg off of the ground without bearing weight thereon.

Kneel push cycle apparatus

A services processor includes an editing unit, which performs various functions for editing data packets, such as packet creation, packet encapsulation, and packet replication.

Services processor having a packet editing unit

In a services processor, a queue operations unit controls the output of processed data packets from the services processor. In accordance with a hybrid list/calendar queue priority scheme, the queue operations unit uses a unique data structure comprising a tree of calendar arrays and queue lists to schedule the data packets for output.

Services processor having a queue operations unit and an output scheduler

The invention provides apparati and methods for processing a packet. The processing is done according to a table and context based scheme.

Table driven programming system for a services processor

The invention provides apparatuses and methods for quickly modifying state information. Preprocessing prepares the state information to be modified. A logic unit modifies the state information. Postprocessing then puts the modified state information in proper form for output.

State record processing

A system for filtering data comprises a filtering database for storing layered rule tables and a data filtering engine coupled to the filtering database for filtering the input data using the layered rule tables. The data filtering engine filters or classifies input data using tests or rules performed on the data elements in the input data. The data elements are segments of data in the input data and are selected from the input data using a data element locator. Preferably, each rule table in the filtering database comprises a data element locator, a default rule, and zero or more filtering rules. The filtering rules comprise the tests or rules that are to be applied to the data elements. Each rule table corresponds to a single data element and each filtering rule in the rule table is to be applied to that data element.

System and method for filtering data

A network services processor receives, stores, and modifies incoming packets and transmits them to their intended destination. The network services processor stores packets as buffers in main and cache memory for manipulation and retrieval. A memory subsystem stores packets as linked lists of buffers. Each bank of memory includes a separate memory management controller for controlling accesses to the memory bank. The memory management controllers, a cache management unit, and free list manager shift the scheduling of read and write operations to maximize overall system throughput. For each packet, packet context registers are assigned, including a packet handle that points to the location in memory of the packet buffer. The contents of individual packets can be accessed through the use of encapsulation pointer registers that are directed towards particular offsets within a packet, such as the beginning of different protocol layers within the packet.

System and method for packet storage and retrieval

An apparatus and method for caching data in an associative memory cache using a single non-overlapping entry, wherein the non-overlapping entry is created from a matching entry and one or more overlapping entries that are stored in a primary associative memory.

Caching associative memory using non-overlapping data

A system and method for determining a best match from a plurality of matches received in response to a search input for an associative memory includes a priority field associated with each data item stored in the associative memory. The priority field corresponds to criteria that is used to order the priority of the data items in the associative memory. A match resolution circuit is coupled to receive match signals from an associative memory, such as a CAM, and the priority fields of the matching data items. The match resolution structure compares the priority fields of the matching data items to determine which data item has the highest priority. The match resolution structure indicates the data item with the highest priority in the priority field as the best match of the associative memory for the particular search input.

Match resolution circuit for an associative memory

A boundary addressable memory (BAM) array comprises a plurality of BAM word modules, each BAM word module comprises a plurality of BAM cells for performing arithmetic comparisons between input data and an upper bound value and a lower bound value stored in each BAM cell to generate a matching signal indicating whether the input data is not greater than the upper bound value and not less than the lower bound value or whether the input data is not greater than the lower bound value and not less than the upper bound value.

Boundary addressable memory

A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR signal line, thereby reducing power dissipation in the wired OR circuit. A common current source coupled to each logic block through a common return path allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.

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San Mateo, CA, United States of America

Walter E Croft