Ing C. Olivetti C., S.p.a.

Olivetti Tecnost S.p.a.

Olivetti Tednost S.p.a.

Walter Cerutti

Gianpiero Bianco

This invention relates to a device for converting bit strings from a first resolution to a second resolution suitable for application, in particular, on peripherals such as printers, scanners or facsimile machines. The device comprises a source register in which a string of bits to be converted is stored by a CPU , a destination register from which the CPU extracts the converted string, and a pair of control registers and which cooperate for converting bit by bit the bit strings from the source register to the destination register . The control registers and , the source register and the destination register operate independently from the CPU used and at a clock rate (clk ) greater than that (clk ) of the CPU , thereby permitting extremely fast conversion times.

Bit string conversion device

This invention relates to a device for controlling the activation of moving elements, such as for example an ink jet type print-head or a sensor of equipment for scanning text and/or images. The device, upon the measurement by means of, for example, the moving element to travel the step P, and the basis of selectively predefined numerical values associated through the control circuit with the time T(p), permits division of the step (p) into a number of n of elementary steps P/n uniformly distributed through the step P, including for high values of the number n. Accordingly by means of the device it is possible to obtain considerable uniform printing or scanning under all conditions and, in particular, when the resolution, which depends on the value of the number n, has to be at its maximum.

Electronic device for the control of moving elements in text and/or image processing equipment

This invention relates to an electronic device, for a fax machine in particular, comprising controlling means ( ) capable of associating compression codes or code words with strings of source information in accordance with a first processing speed, and storing means, for example shift registers ( ) capable of appending the code words to one another so as to form blocks of compressed information, in accordance with a second processing speed, greater than the first. The device is also capable of &ldquo;extracting&rdquo; the single code words from blocks of compressed information at this second processing speed. By way of the technique of using different processing speeds, the device makes it possible to obtain total speeds of compression and/or decompression of the information respectively to be transmitted and/or received much greater than those obtainable up to now with the known devices.

Device for compressing/decompressing bit strings

A memory addressing device for data processing apparatus addresses in sequence and in a burst a series of memory locations in a single addressing period of a central processing unit. The device comprises enabling circuits to set a central processing unit (CPU) to a burst transfer cycle and to keep a memory control unit (MCU) in a waiting state during the burst transfer. An address generator circuit is capable of generating in sequence a series of memory address codes to address a series of locations in the memory (RAM) during the burst transfer cycle. A multiplexer circuit sends to the memory either the address code of the address generator or that of the memory control unit during the burst cycles and the normal cycles respectively. The device is particularly suitable for use in personal computers with high data transfer rates.

Memory addressing device

The electronic circuit connects a processor to a high-capacity memory of 1 Megabyte. The processor may be of the 8 bit type, with a 16 bit address bus (A0-A15). The memory is subdivided into 256 segments each having a capacity of 4 Kbytes which can be directly addressed by the processor by means of 12 (A0-A11) of the 16 lines of the address bus. An auxiliary RAM is interposed between the processor and has 1 Mbyte memory and comprises sixteen 8 bit registers (R0-R15), which can be addressed by means of the other four lines (A12-A15), of the address bus. By means of the 8 bit data bus (D0-D7), the 16 registers of the RAM store the numbers of those 16 segments out of the 256 segments of the 1 Mbyte memory, which from time to time are connected to the processor. In this way the processor, while being able to address only 64 Kbytes of memory at a time, has the whole of the 1 Mbyte memory available. The circuit can be applied to data processing and word processing units and electronic typewriters.

Electronic circuit for extending the addressing capacity of a processor

In an electronic typewriter having a printing device of the daisywheel type, the direct current electric motors which control the rotation of the character-carrying element, the movement of the carriage along the various printing positions and the rotation of the platen roller for line spacing are associated with corresponding transducers which detect the angular position thereof, and are actuated by a single integrated circuit connected to a microprocessor by an address and data bus (43). The microprocessor determines, for each of the motors, the angular amplitude of the rotary movement and the time required to cover each of the elementary angular distances, in accordance with a given speed law and addresses with data, including the said time, a plurality of circuit modules (B1, B2, B3) individual to the motors. The modules issue motor command signals (e.g. M11, M21, M31). Checking as between the actual speed and the desired or theoretical speed is effected by the modules of the integrated circuit using the timing signals (e.g. STA 1, STB 1) generated by the transducers connected to the motors. The modules send back interrupt signals (INT 1, INT 2, INT 3) which provide interrupt vectors (46) for the microprocessor, enabling the microprocessor to determine the new data to be sent to the modules.

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Ivrea, Italy

Walter Cerutti