Motorola Corporation

Other

Walter C Seelbach

Robert P Dixon

Mark S Birrittella

Kevin L McLaughlin

Douglas W Schucker

Robert R Marley

Daniel N Koury, Jr

Ahmad H Atriss

Scott G Nogle

Robert H Reuss

Thomas P Bushey

Steven Peter Allen

Ward D Parkinson

Pat Hickman

Boyd K Hansen

Gerald Lee Walcott

Danny J Molezion

Golnaz Kaveh

David B Weaver

Paul Andrew Nygaard

A voltage boosting circuit which derives an output voltage than is substantially twice the magnitude of a supply voltage applied thereto. The voltage boosting circuit consists of complementary acting boost circuits each having a pair of switches (42A, 52A; 42B, 52B) connected between an input of the voltage boosting circuit, at which is applied the supply voltage, and an output at which the output voltage is produced. Boost capacitors (48A, 48B) are connected between the respective switches of the complementary boost circuits and the switches of the these circuits are opened and closed out of phase with respect to each other in response to clocking signals being applied thereto such that a boosted output voltage is produced during each half cycle of the clocking signals.

Complimentary double pumping voltage boost converter

A low voltage submicron CMOS circuit (10) for providing an output bandgap voltage (V.sub.BG) that is substantially independent of temperature and power supply variations has been provided. The CMOS circuit utilizes parasitic transistors (28-30) to create a delta voltage that has a positive temperature coefficient across a differential pair of NMOS transistors (14, 16). This delta voltage is then converted into differential currents which are amplified and mirrored and summed together to provide an output current (I.sub.O) that has a positive temperature coefficient. This output current is then passed through a series network including a resistor element (52) and a parasitic PNP junction transistor (31) to provide a bandgap voltage of 1.2 volts wherein the voltage across the resistor element has a positive temperature coefficient and the voltage across the parasitic PNP junction transistor has an inherent negative temperature coefficient.

CMOS circuit for providing a bandcap reference voltage

A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.

Voltage level translator circuit with cascoded output transistors

A bipolar complementary metal oxide semiconductor (BICMOS) sense circuit for sensing data on read data lines during a read cycle of a memory comprises a load portion and a sense amplifier portion. In one form, the load portion couples true and complement read data lines to a first voltage in response to a start of a read cycle. When the true and complement read data lines exceed a predetermined voltage, the sense amplifier is enabled. The load portion becomes inactive when the voltage on the read data lines reaches approximately the first voltage. Then a selected memory cell provides a differential voltage on a bit line pair, which is coupled to the read data lines, indicating the contents of the selected memory cell. The sense amplifier provides a differential current onto a corresponding read global data line pair in response to the differential voltage. At the termination of the read cycle, the load portion becomes active again and couples the read data lines to a second voltage to disable the sense amplifier. The predetermined voltage is between the first voltage and the second voltage. The circuit increases the speed of the sensing function over a CMOS design, while keeping power consumption to a minimum. In another form, the sense circuit generates a read sense voltage that is substantially independent of non-tracking process variations between P-channel and N-channel field-effect transistors.

BICMOS sense circuit for sensing data during a read cycle of a memory

A source terminated transmission line driver circuit having an output coupled to a transmission line through a resistor is provided. The driver circuit has a gate circuit for providing first and second signals and a pulse generator circuit responsive to the second signal of the gate circuit for providing a pulse current at an output when the second signal is switching from a first logic state to a second logic state and for otherwise providing a quiescent current at the output. The driver circuit also has a first circuit responsive to the first output signal of the gate circuit for sourcing current to the output of the source terminated transmission line driver circuit, the first circuit being responsive to the second output signal of the gate circuit for sinking an adjustable current at the output of the source terminated transmission line driver circuit. The first circuit has a first transistor having a collector, a base and an emitter, the emitter being coupled to the output of the source terminated transmission line driver circuit, the base being coupled to receive the first signal of the gate circuit, and the collector being coupled to the first supply voltage terminal, a second transistor having a collector, a base and an emitter, the emitter of the second transistor being coupled to the output of the source terminated transmission line driver circuit, the base of the second transistor being coupled to the output of the pulse generator circuit, the collector being coupled to a second supply voltage terminal, a third transistor having a collector, a base and an emitter, the collector of the third transistor being coupled to the first supply voltage terminal, the base of the third transistor being coupled to the base of the first transistor, and a fourth transistor having a collector, a base and an emitter, the collector and base of the fourth transistor being coupled to the emitter of the third transitor, the emitter of the fourth transistor being coupled to the base of the second transistor.

Source terminated transmission line driver

A BiMOS voltage reference circuit which includes a bandgap circuit for providing a predetermined voltage at an output of the circuit that is independent of temperature. A start-up and bias circuit coupled to the bandgap circuit for providing a start-up current to the bandgap circuit during power-up and for providing a bias current to the bandgap circuit after power-up. A feedback circuit coupled to the bandgap circuit for maintaining the bias current to the bandgap circuit independent of power supply variations wherein the predetermined voltage at the output of the circuit is also independent of power supply variations as well as temperature.

Voltage reference circuit with power supply compensation

A circuit is provided that generates a predetermined regulated voltage between first and second terminals that is positioned between first and second power supply voltage rails wherein the predetermined regulated voltage is substantially independent of temperature and power supply variation. The circuit includes a bandgap circuit for providing a predetermined reference potential that is substantially independent of temperature and power supply variation. A resistive circuit provides first and second voltages which are referenced with respect to the first supply voltage rail. A level translator circuit translates the second voltage provided by the resistive circuit to a third voltage which is referenced with respect to the second supply voltage rail. First and second operational amplifier circuits are provided for respectively transferring the first and third voltages respectively to first and second terminals wherein a voltage developed between the first and second terminals is substantially equal to the predetermined reference voltage of the bandgap circuit.

Voltage regulator and method for submicron CMOS circuits

A voltage translator circuit is responsive to applied ECL input signals for providing corresponding CMOS level logic output signals therefrom. The voltage translator circuit includes a pair of substantially identical translator circuits each having an input coupled to an input of the voltage translator circuit and which are supplied a regulated voltage such that the operation thereof is substantially independent of negative power supply variations and temperature. An output stage is coupled between the output of one of the pair of translator circuits and the output of the voltage translator circuit while the output of the other translator circuit is coupled to the output of the voltage translator circuit in order to provide the CMOS level logic output signals.

ECL to CMOS logic translator

A high speed voltage translator provides a CMOS output signal in response to an ECL input signal which is applied to an input stage coupled between first and second power supply conductors wherein the potential developed at the output of the input stage is independent of variations in the power supply voltage. The translating stage is coupled between said first and second power supply conductors and is responsive to the potential developed at the output of the input stage for conducting a predetermined current therethrough. A feedback signal proportional to the magnitude of the predetermined current flowing through the translating stage is generated to control the potential developed at the output of the input stage so as to maintain the predetermined current at a low value to reduce the power consumption of the voltage translator.

High speed ECL to CMOS translator having reduced power consumption

An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a voltage thereto in response to a first signal from a logic circuit. A pull-down transistor is coupled to the output terminal for selectively sinking a current therefrom in response to a second signal. A comparator circuit is coupled to the pull-down transistor, the logic circuit, and the output terminal, for selectively providing the second signal in response to the first signal and an output voltage on the output terminal.

Load controlled ECL transient driver

A BICMOS driver circuit is provided having high input impedence and high output current drive with low static power dissipation that provides supply voltages and full logic output voltage swing for circuits having submicron dimensions. An inverter circuit is coupled to a voltage divider circuit and the input terminal for inverting the input signal. A complementary emitter follower circuit is coupled to an output terminal for providing a digital output signal. A current source circuit is coupled to the complementary emitter follower circuit and the input terminal for sourcing current to the complementary emitter follower circuit in response to the input signal. A bipolar bias circuit is coupled to the complementary emitter follower circuit and the inverter circuit for biasing the complementary emitter follower circuit in response to an inverted input signal.

BICMOS driver circuit including submicron on chip voltage source

A BIMOS amplifier having feedback clamping the amplifier's input to a predetermined voltage, minimizes input signal voltage excursions in the presence of large load capacitances. A pair of differentially coupled NPN transistors in response to first and second inputs drive a pair of emitter follower NPN transistors. First and second MOS transistors responsive to first and second enable signals are coupled between the ouptut from each of the emitters of the emitter follower transistors and the first and second inputs, respectively.

BIMOS memory sense amplifier system

A BIMOS memory cell is formed by providing a CMOS static RAM cell with an additional NPN bipolar transistor to provide additional drive current during the read cycle to improve the read time of the memory cell.

CMOS static ram cell provided with an additional bipolar drive transistor

A circuit is described that provides a quick charge and discharge of a row of memory cells. A first transistor has its collector-emitter path coupled between a first voltage and a row of memory cells, and a base coupled to an input terminal. A second transistor has its collector-emitter path coupled to the first voltage by a resistor and to a voltage level setting device, and a base coupled to the input terminal. A third transistor has its collector-emitter path coupled between the row of memory cells and a second voltage, and a base coupled to a voltage level shifting device. As the row of memory cells are selected, the third transistor becomes less conductive, thereby sinking less current from the row of memory cells and allowing the inherent capacitance of the row of memory cells to charge more quickly. As the row of memory cells are deselected, the third transistor becomes more conductive, thereby sinking more current from the row of memory cells and discharging the inherent capacitance more quickly.

Circuit for charging and discharging a row of memory cells

A transient driver circuit for use with a logic circuit having an emitter-follower output stage that sources current to a load connected to an output thereof in response to an applied logic signal being at a first logic level. The transient driver circuit includes a first NPN transistor the collector-emitter path of which is coupled between the output of the logic circuit and the negative power supply rail, a second NPN transistor having its collector-emitter path couple between a positive power supply rail and the collector of the first NPN transistor and its base adapted to receive the logic signal and feedback circuitry that is responsive to a rise in the collector voltage of the second NPN transistor occurring as the logic signal switches to a second logic level for supplying current drive to the base of the first NPN transistor thereby turning it on to sink a large transient current at the output of the logic circuit.

Growing community of inventors

Fountain Hills, AZ, United States of America

Walter C Seelbach