Spansion Llc.

Monterey Research, LLC

Agere Systems Inc.

Walter Allen

Robert France

Sunil Atri

Joseph Khatami

Robert Alan Reid

James Byrd

A novel end assembly for canes and other walking aids having a linear adjustable hydraulic shock absorber threaded into the distal end of the cane and facility for mounting various cane and walking aid ends.

Cane with linear adjustable hydraulic shock absorber end

Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

Relocating data in a memory device

A method and apparatus for storing a disk drive media defect table or list. Defect table entries for a subject disk track are stored on the subject track and retrieved for determining defective sectors only when the subject track is accessed for a data read or write operation.

Track defect map for a disk drive data storage system

A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data.

Data commit on multicycle pass complete without error

Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.

Address caching stored translation

Systems and/or methods that facilitate transferring data between a processor component and memory components are presented. A transfer controller component facilitates controlling data transfers in part by receiving respective subsets of data from respective memory components and arranging the respective subsets of data based in part on a desired predefined data order. The processor component generates a transfer map that includes information to facilitate arranging data in a predefined order. The processor component generates respective subsets of commands that are provided to queue components in respective memory components to retrieve desired data from the respective memory components. Each memory component services the commands in its queue component in an independent and parallel manner, and transfers the data retrieved from memory to the transfer controller component, which can arrange the received data in a predefined order for transfer to the processor component.

Command queuing for next operations of memory devices

Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offloaded and controlled by the memory component(s). A search component searches pages in the memory array to facilitate locating a page of data associated with an LBA stored in the memory component. The search component can retrieve a portion of a page of data in a block in the memory component to facilitate determining whether the page contains an LBA associated with a command based in part on command information. The search component can search pages in the memory component until a desired page is located or a predetermined number of searches is performed without locating the desired page.

Memory array search engine

Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation.

Physical block addressing of electronic memory devices

Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.

Translation management of logical block addresses and physical block addresses

Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented.

Bit map control of erase block defect list in a memory

One or more bits are added to the embedded repeatable runout correction (ERRC) bit pattern of a servo field so that errors in ERRC bit patterns can be detected and in certain cases corrected. If four bits are added, a single bit error in an ERRC bit pattern can be detected and corrected. If five bits are added, two bit errors in the ERRC bit pattern can be detected. In accordance with the preferred embodiment, the invention uses a single encode table and a single decode table to encode the ERRC pattern to be written to the disk and to decode the ERRC pattern read back from the disk.

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Wellington, CO, United States of America

Walter Allen