Xilinx, Inc.

Walter A Manaker, Jr

Jay T Young

Brian Philofsky

Scott J Campbell

Carl M Stern

Jaime D Lujan

William R Troxel

Mario Escobar

Eric Ford Dellinger

David Wayne Bennett

Jindrich Zejda

Ilya K Ganusov

Sankaranarayanan Srinivasan

Benjamin S Devlin

Satish B Sivaswamy

Salim Abid

Atul Srinivasan

Nicholas A Mezei

Matthew Bixler

David A Ewing

Approaches for processing a circuit design include determining pin slack values for pins of the circuit elements in the circuit design. A processor selects a subset of endpoints based on pin slack values of the endpoints being in a critical slack range and determines startpoints of the circuit design that are in respective critical fanin cones. For each endpoint of the subset, the processor determines an arrival time from each startpoint in the respective critical fanin cone and determines for each startpoint-endpoint pair, a respective set of constraint values as a function of the respective arrival time from the startpoint. The processor generates a graph in the memory circuit from the startpoint-endpoint pairs. First nodes in the graph represent the startpoints and second nodes in the graph represent the endpoints, and values in the respective set of constraint values are associated with edges that connect the nodes.

Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design

Various approaches for incrementally updating the timing of an implementation of an electronic circuit design are disclosed. In one approach, a subset timing graph is selected from a primary timing graph. Alternative subset timing graphs are generated that are functionally equivalent and structurally different with respect to the selected subset timing graph. For each of the alternative timing graphs, a respective timing metric is determined. The determined timing metrics and a timing metric for the selected subset timing graph are compared. An alternative timing graph is selected in response to the comparison. Structurally different portions of the selected one of the one or more alternative timing graphs are verified with regard to the design constraints. The structurally different portions are stored to the primary timing graph.

Efficient timing graph update for dynamic netlist changes

The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not include unnecessary skew values, resulting in a skew value without pessimism. A setup slack determination ensures that data launched or transmitted from a source register reaches the destination register within a specified maximum cycle time and is defined as the difference between a minimum (early) destination time and a maximum (late) source time without unnecessary skew values. A hold check slack determination ensures the data does not 'race' from the source register to the destination register on the same clock edge and is calculated as a difference between a maximum (late) destination time and a minimum (early) source time without unnecessary skew values. A circuit's operational frequency and layout are based upon the method for calculating skew.

Efficient method for computing clock skew without pessimism

Method for computing hold and setup slack without pessimism

A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.

Timing annotation accuracy through the use of static timing analysis tools

A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the minimum clock path delay for a destination register of the circuit design. The method further can include adjusting a register timing parameter for the destination register according to the difference and performing a timing verification on the destination register using the adjusted register timing parameter.

Annotating timing information for a circuit design for increased timing accuracy

Various embodiments of the invention determine whether paths of a first graph satisfy a constraint based on a plurality of sub-graphs of the first graph. Each graph is a directed acyclic graph of nodes and arcs. The first graph and a second graph are generated in a memory arrangement, with the first graph and the second graph having a shared sub-graph, and each path of the paths of the first graph is constrained by the constraint unless the path is a path of the second graph. The plurality of sub-graphs of the first graph are generated in the memory arrangement with each of the plurality of sub-graphs not including any path of the second graph and each of the paths of the first graph that is not a path of the second graph being included in at least one of the plurality of sub-graphs.

Representation of a relaxation of a constraint by graph replication

Method and apparatus for phase-timing compensation is described. More particularly, a clock source and a clock sink of a path are identified for phase-timing compensation for a design. An absolute path slack is obtained, and phase offset of the clock source relative to the clock sink is determined. A normalizing factor responsive to the phase offset is generated. A normalized slack is computed using the absolute path slack and the normalizing factor.

Path slack phase adjustment

A device independent, frequency driven layout system and method for field programmable gate arrays ('FPGA') which allow for a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGA device to operate at the specified frequencies. Actual net, path and skew requirements are automatically generated and fed to the place and route tools. The system and method of the present invention evaluates the frequency constraints, determines what delay ranges are acceptable for each electrical connection and targets those ranges throughout the layout.

Growing community of inventors

Boulder, CO, United States of America

Walter A Manaker, Jr