Silicon Aquarius, Inc.

Walland Bart Holland

Stephen Earl Seitsinger

A memory,having an array,of rows and columns of dynamic memory cells,cells,of each row coupled to a refresh wordline,and an access wordline,and cells,of each column coupled to a refresh bitline,and an access bitline,Refresh circuitry,refreshes selected rows of cells corresponding to a refresh wordline,and a corresponding one refresh bitline,Access circuitry accesses selected cells of a selected row using corresponding access wordline,and corresponding one of the access bitlines,The access circuitry includes a new address detector of,for detecting receipt of a new address of said memory, a row decoder,for selecting access wordline in response to receipt of the new address and access sense amplifiers,and an access column decoder,accesses at least one cell along the selected wordline,using the corresponding access bitline

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Dallas, TX, United States of America

Walland Bart Holland