International Business Machines Corporation

Wallace Sharp

David Andrew Schroter

Debapriya Chatterjee

John Andrew Schumann

Larry Scott Leitner

Bryant Cockcroft

John Martin Ludden

Darin Marcus Greene

Examples described herein provide a computer-implemented method that includes executing, by the microprocessor, instructions in an instruction stream of the microprocessor. The method further includes triggering, by control logic of the microprocessor, error condition monitoring logic. The method further includes executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.

Software-invisible interrupt for a microprocessor

A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.

Method and apparatus for controlling program instruction completion timing for processor verification

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Round Rock, TX, United States of America

Wallace Sharp