Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Other

Verizon Patent and Licensing Inc.

Avago Technologies International Sales Pte. Limited

Movandi Corporation

Walid Nabhane

Veronica Alarcon

Mark Norman Fullerton

Chih-Tsung Hsieh

Hao-zheng Lee

Xiaoxin Qiu

Jason C Demas

Mark David Rutherford

Love Kothari

Pascal G Finkenbeiner

Ajmal A Godil

Ronak Subhas Patel

Ahmadreza Rofougaran

Maryam Rofougaran

Brima Babatunde Ibrahim

Sam Gharavi

Reid Andersen Schlegel

Vadim Bishtein

Ming-Hung Hung

Andrew Nicholas Toth

David Chang

Robert Stewart

Chenmin Zhang

Christopher Emmons

Arun Palaniappan

Zhongmin Zhang

Narayan Prasad Ramachandran

Raghu Mulagada

Jhan-Li Wu

Lionel Maurice Federspiel

Yi Ting Chen

Mohsen Pourkhaatoun

Christopher Adrain Den Haan

Wan-Jong Kim

Chun-Nan Ke

John Russell Platenak

John Niemasz

Serge Van Steenkiste

A repeater device for New Radio (NR) communication, includes a baseband processor that establishes a communication link with a base station and decodes control information that is received from the base station through a control channel. The baseband processor further aligns a timing reference of the repeater device with that of an NR cell frame for an uplink or a downlink time division duplex (TDD) switching, based on the decoded control information. The baseband processor further selects and forms one or more donor beams of RF signals at a donor side of the repeater device and one or more service beams of RF signals at a service side of the repeater device, based on the decoded control information and the aligned timing reference with that of the NR cell frame for the uplink or the downlink TDD switching for communication in an NR frequency band.

Repeater device for 5G new radio communication

A device may include a housing with a plurality of top openings provided in a top portion of the housing and a plurality of bottom openings provided in a bottom portion of the housing. The device may include one or more internal components provided within the housing to provide a wireless service. The device may include a rotation extension connected to the bottom portion of the housing and configured to rotatably attach to a bracket that mounts the device to an object. The device may include a connector connected to the rotation extension and configured to receive a cable that provides communication signals to and from the device.

Mounting systems for a wireless network device

Systems and methods of handling satellite channel and LTE coexistence are provided. A first device can identify at least one first frequency band. The first device can determine that at least one second frequency band of a plurality of second frequency bands overlaps with the at least one first frequency band. In response to determining that the at least one second frequency band overlaps with the at least one first frequency band, the first device transmits a message including an identifier of the first device and an indication of the at least one second frequency band to a second device. The second device receives the message. The second device, in response to receiving a channel request from the first device, allocates, from the plurality of second frequency bands, a second frequency band different from the at least one second frequency band.

Satellite channel and LTE coexistence

Systems and methods disclosed herein facilitate communication in a communication network amongst entities by way of publicly-available identifiers. In an embodiment a first entity sends to a node in the communication network a first electronic communication which includes a public or private identifier for the first entity and a public identifier for a second entity which is a publicly-available identifier observable by the first entity and may include, for example, a vehicle identifier, a geographic locator, a venue identifier, a seating locator, a wearable identification device, and combinations thereof. The node determines a private identifier for the second entity based on the received public identifier for the second entity and sends a second electronic communication to the second entity which includes at least one of the public or private identifier for the first entity and at least one of the public or private identifier for the second entity.

System and method for communication amongst entities by way of public identifiers

A voltage dedicated charger apparatus includes an AC-to-DC converter circuit, a pair of switches, and a controller block. The AC-to-DC converter circuit converts an AC input voltage to a DC output voltage. The pair of switches is operable to isolate a pair of data ports from the AC-to-DC converter circuit. The pair of data ports includes a DP port and a DN port. The controller block includes a monitor circuit, a transceiver, and a control circuit. The monitor circuit monitors the DP and DN ports of the apparatus. The transceiver receives one or more messages form a charge-receiving device and communicate data to the charge-receiving device. The control circuit controls operation of the pair of switches based on a signal from the monitor circuit.

Smart voltage dedicated charger system

Aspects of enhanced recovery mechanisms are described. A predetermined operating parameter for a power rail is set at the outset of system start. Afterwards, a processor is released to start with a power management circuit. In turn, the power management circuit receives a default operating parameter for the power rail from the processor, and stores the default operating parameter. The power management circuit also receives a runtime operating parameter for the power rail from the processor and modifies the operating parameter for the power rail according to the runtime operating parameter. If an error condition in the processor is encountered, the power management circuit may modify the operating parameter for the power rail according to the default operating parameter in response to a reset control signal from the processor. Use of the default operating parameter for the power rail may assist the processor to recover from the error condition.

Enhanced recovery mechanisms

A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.

Clock domain crossing serial interface

Aspects of power mode register reduction and power rail bring up enhancements are described. In one embodiment, an operating parameter for a first power rail is set by power management circuit according to a predetermined programmed setting. In connection with a wait time, the power rail is enabled, and a processor is released to start. In turn, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail is received from the processor over a high speed interface. By accessing a grouped operating register for a group of power rails, the processor can update or modify settings of an entire group of power rails at one time. In connection with the processor, the power management circuit can power up a plurality of power rails in a flexible and efficient manner.

Power mode register reduction and power rail bring up enhancement

Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.

Charger detection and optimization prior to host control

Aspects of dynamic power profiling are described herein. In various embodiments, a current sense operating mode is set for a current sense circuit, and the current sense circuit is enabled for operation. The current sense circuit senses an amount of current supplied by at least one of a plurality of power rails based on the current sense operating mode. The current sense circuit also accumulates and stores a value of the amount of current over a period of time. In certain aspects, a system controller averages the value of the amount of current based on the period of time. The current sense circuit may be configured to operate in various modes of operation including single or scan rail modes of operation, and the average of the value of the amount of current may be evaluated based on the modes of operation of the current sense circuit and/or the system.

Dynamic power profiling

Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.

Clock domain crossing serial interface, direct latching, and response codes

Growing community of inventors

Long Valley, NJ, United States of America

Walid Nabhane