Intel Corporation

Other

Waleed S Almulla

Bradley G Heaney

Meeling Roberts

Ronald J Mayer

Gloria Leong

A low power consumption component which operate at a high frequency is provided by separating out those critical signal paths which acquire a higher voltage to operate below a maximum propagation delay requirement and operating the remainder of the devices of the component at a lower power supply to minimize overall power consumption of the component.

Method and structure for improving power consumption on a component

A stand alone Personal Electronic Telephone Directory (PETD) apparatus is provided, that includes an internal telephone line segment, an off hook circuit, a Dual Tone Multi-Frequency (DTMF) receiver, a ring detection circuit, a micro-controller, a memory, a speech synthesizer, and a DTMF generator. The PETD apparatus is a stand alone device intended for connection to an individual user's home telephone line, and for access by using a common touch tone ('DTMF') telephone. The user can access the memory of the PETD apparatus of the present invention locally or remotely. Then the user can issue coded instructions by simply pressing the keys of the DTMF telephone. By giving specific instructions, the user is allowed to add, retrieve or delete data from the memory of the PETD apparatus. The PETD apparatus communicates with the user by voice, generated by the speech synthesizer. Additionally, if the PETD apparatus is being accessed locally, then the user can instruct it to dial automatically the telephone number retrieved from the memory, so that the user can continue automatically with a telephone call to the retrieved telephone number.

Personal electronic telephone directory apparatus with remote

An apparatus having a 3.3 volt power supply and a 5 volt power supply, wherein digital signals are processed on a 3.3 volt basis which are translated to a 5 volt basis by a voltage translation circuit before being output. The voltage translator is comprised of an inverter for inverting an input signal. The inverter is powered by the 3.3 volt power supply. A p-channel transistor having its source coupled to the 5 volt power supply and its gate driven by the output of the inverter is implemented. When the inverter generates a low logic, the p-channel transistor is turned on and outputs 5 volts. An n-channel transistor having its source coupled to ground and its gate driven by the output of the inverter is also implemented. When the output of the inverter is 3.3 volts, the n-channel transistor is turned on, which pulls the output to ground. Therefore, when the input signal is at 3.3 volts, a 5 volt signal is output from the voltage translation circuit. When the input signal is at 0 volts, the output signal is, likewise, at 0 volts.

Apparatus for translating logic signal levels from 3.3 volts to 5 volts

An input buffer capable of operating at a plurality of power supply levels. The input buffer of the present invention includes input logic that receives the data and has pull-up and pull-down devices that are coupled together in series as an inverter to generate a signal indicative of the data input. The input buffer also includes a mechanism for adjusting the strength of the pull-up and pull-down devices independent of each other so that the trip point and the propagation delay remain the same for the different power supply levels. This allows the input buffer to be CMOS and TTL compatible for all inputs. The input buffer also includes output logic which outputs the data in response to the signal from the input logic.

Programmable input buffer

A power supply level detector. The power supply level detector includes a modified differential amplifier which compares a first power supply level at a known voltage range with a second power supply level capable of being at multiple power supply levels. The result of the comparison is a signal which indicates the level of the second power supply.

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Folsom, CA, United States of America

Waleed S Almulla