Infineon Technologies Ag

Infineon Technologies Austria Ag

Waldemar Jakobi

Christoph Koch

Juergen Hoegerl

Ivan Nikitin

Olaf Hohlfeld

Thorsten Scharf

Andreas Grassmann

Tomas Manuel Reiter

Andre Arens

Christian Schweikert

Egbert Lamminger

Michael Niendorf

Peter Luniewski

Michael Leipenat

Michael Fuegl

Marco Bäßler

Markus Neubert

A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.

Semiconductor package with balanced impedance

A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

Power semiconductor package having first and second lead frames

A power semiconductor module arrangement includes a power electronics substrate comprising a first DC voltage pad, a second DC voltage pad, a first load pad, and a second load pad, first and second transistor dies mounted on the first load pad, third and fourth transistor dies mounted the first DC voltage pad, the first and second transistor dies collectively form a first switch, the third and fourth transistor dies collectively form a second switch, the first and second DC voltage pads are arranged such that a DC supply impedance for a first commutation loop that flows through the first and third transistor dies matches a DC supply impedance for a second commutation loop that flows through the second and fourth transistor dies, and an impedance of a first load connection to the third transistor die is greater than an impedance of a second load connection to the fourth transistor die.

Power module layout for symmetric switching and temperature sensing

A power semiconductor module includes a power semiconductor chip arranged between a first substrate and a second substrate and electrically coupled to the substrates, and a temperature sensor arranged between the substrates and laterally besides the power semiconductor chip such that a first side of the temperature sensor faces the first substrate and a second side of the temperature sensor faces the second substrate. A first electrical contact of the temperature sensor is arranged on the first side and electrically coupled to the first substrate. A second electrical contact of the temperature sensor is arranged on the second side and electrically coupled to the second substrate.

Power semiconductor module and method for fabricating the same

A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks, and individual semiconductor chips each having a controllable semiconductor element, first and second load electrodes, and a control electrode. The first conductor track has a base section and further sections extending from the base section. The second conductor track has sections. The further sections of the first conductor track and the sections of the second conductor track extend parallel to one another in a first direction at least over a same lateral dimension of the individual semiconductor chips. The further sections of the first conductor track alternate with the sections of the second conductor track in a second direction orthogonal to the first direction. The individual semiconductor chips are arranged on the sections of the second conductor track. The first load electrodes are connected to the further sections of the first conductor track.

Semiconductor arrangement having a circuit board with a patterned metallization layer

A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks. The first conductor track has a base section and first, second and third sections, the third section arranged between the first and second sections. The second conductor track has first and second sections. The first section of the second conductor track is arranged between the first and third sections of the first conductor track. The second section of the second conductor track is arranged between the second and third sections of the first conductor track. The third section of the first conductor track is arranged between the first and second sections of the second conductor track. First and second subsets of semiconductor chips are arranged on the first section of the second conductor track. Third and fourth subsets of semiconductor chips are arranged on the second section of the second conductor track.

Semiconductor arrangement with reliably switching controllable semiconductor elements

Growing community of inventors

Soest, Germany

Waldemar Jakobi