Fujitsu Corporation

Fujitsu Microelectronics Limited

Waichiro Fujieda

Shinya Fujioka

Yoshitaka Takahashi

Hiroyuki Fujimoto

Tomohiro Nakayama

Masanori Nagasawa

Atsushi Fujii

Yutaka Fukutani

Masakazu Kimura

Seizi Hirayama

Arayama Youji

Tutomu Taniguti

Kota Hara

Hiroyuki Kobayashi

Shinichi Yamada

Shinichiroh Ikemasu

Hitoshi Ikeda

Toshiya Uchida

Yasuharu Sato

Tadao Aikawa

Toru Koga

Yoshiaki Okuyama

Yoshimasa Yagishita

Masaki Okuda

Shusaku Yamaguchi

Katsuhiro Mori

Yoshihide Bando

Masahiro Yada

A plurality of switch circuits are disposed so as to correspond to a plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. A setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. A switch control circuit turns on each of the plurality of switch circuits according to a first control signal for indicating an operation state of the plurality of circuit blocks when each of the plurality of switch circuits is set in a valid state by the setting circuit and turns on each of the plurality of switch circuits regardless of the first control signal when each of the plurality of switch circuits is set in an invalid state by the setting circuit.

Semiconductor device and electronics device

First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.

Semiconductor memory having a dummy signal line connected to dummy memory cell

A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

Memory circuit having parity cell array

A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Semiconductor memory

A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N&equals;L&times;M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.

Memory circuit having compressed testing function

A semiconductor memory device having a self-refresh function includes a detection circuit detecting a change of an output enable signal and generating a state transition detection signal, and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.

Semiconductor memory device

An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.

Semiconductor memory and method of operating same

The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.

Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations

A semiconductor device, comprising a stabilized timing circuit for regulating the phase of each of first and second clocks complementary with each other input from an external source and generating each of first and second internal clocks delayed by a predetermined phase, is disclosed. The stabilized timing circuit includes a clock input circuit unit for receiving the first and second clocks complementary with each other, and a dummy input circuit unit for receiving a first feedback clock and a second feedback clock complementary with each other and having the delay time equivalent to the delay time of the first and second clocks in the clock input circuit unit.

Semiconductor device

A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

Programmable semiconductor memory device

Growing community of inventors

Kawasaki, Japan

Waichiro Fujieda