Other

Texas Instruments Corporation

Fuji Electric Co., Ltd.

Semiconductor Components Industries, LLC

University of Toronto

Asahi Kasei Microdevices Corporation

Asahi Kasei Emd Corporation

Kapik Inc.

Wai Tung Ng

Yan-Fei Liu

Yue Fu

Zhanming Li

Oh-Kyong Kwon

Satwinder S Malhi

Taylor R Efland

Michael C Smayling

Roy Clifton Jones, Iii

Hao Wang

William Martin Snelgrove

Olivier Trescases

Tetsuya Kawashima

Masahiro Sasaki

Jing Wang

Robert Neil McKenzie

Clement A Salama

Haruhiko Nishio

Ivan Kalastirsky

Huaping Xu

Guo Wen Wei

Jeewika Chandanie Ranaweera

Elvira Gulersen

Guanhou Luo

Kendy Ng

A packaged GaN semiconductor device with improved heat dissipation is provided. A GaN device is packaged on a printed circuit board (PCB) with a vertical side of the device, and optionally the back side of the device, in thermal contact with the PCB. The packaging is compatible with surface mount technologies such as land grid array (LGA), ball grid array (BGA), and other formats. Thermal contact between the PCB and a vertical side of the device, and optionally the back side of the device, is made through solder. The solder used for the thermal contact may also connect a source terminal of the device, which also improves electrical stability of the device. The packaging is particularly suitable for GaN HEMT devices.

Vertical-side solder method and package for power GaN devices

Use of gallium nitride (GaN) semiconductor material for power devices is challenging due to low yield caused by high defect density on the wafer. Device layout on the wafer, chip probing, and device packaging increase the yield of large area power devices. Device dies containing a plurality of lower-power sub-devices are used to achieve high power ratings, by connecting only functional sub-devices together in the package, while being tolerant of defective sub-devices by selectively excluding the defective sub-devices. The packages and methods are particularly relevant to GaN power switching devices such as high electron mobility transistors (GaN HEMT).

Defect-tolerant layout and packaging for GaN power devices

A gate driver circuit for a gallium nitride (GaN) power transistor includes a RS-flipflop that receives a first pulse train at an S input terminal and a second pulse train at an R input terminal, and produces an output pulse train, and an amplifier that amplifies the output pulse train and produces a gate driver signal for the GaN power transistor. The RS-flipflop and the amplifier may be implemented together on a GaN monolithic integrated circuit, optionally together with the GaN power transistor. The GaN power transistor may be a high-side switch of a half-bridge circuit. The RS-flipflop may be implemented with enhancement mode and depletion mode GaN high electron mobility transistors (HEMTs). Embodiments avoid drawbacks of prior hybrid (e.g., silicon-GaN) approaches, such as parasitic inductances from bonding wires and on-board metal traces, especially at high operating frequencies, as well as reduce implementation cost and improve performance.

High-side gate driver for gallium nitride integrated circuits

An audio amplifier system includes a delta-sigma modulator configured to receive an m-bit digital audio input signal and to generate a pulse density modulated signal based on the m-bit digital audio input signal. An analog power stage is coupled to the delta-sigma modulator to receive the pulse density modulated signal and amplify the pulse density modulated signal to generate an amplified pulse density modulated signal. A feedback circuit is coupled to the delta-sigma modulator and the analog power stage. The feedback circuit is configured to receive the amplified pulse density modulated signal and the pulse density modulated signal and to determine a digital error signal representative of a difference between the amplified pulse density modulated signal and the pulse density modulated signal. The feedback circuit is further configured to provide the digital error signal to the delta-sigma modulator for applying the digital error signal to a representation of the m-bit digital audio input signal.

Amplifiers with delta-sigma modulators using pulse-density modulations and related processes

Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.

High power gallium nitride devices and structures

This invention relates to interdigitated electrodes for power electronic and optoelectronic devices where field and current distribution determine the device performance. Described are geometries based on rounded asymmetrical fingers and electrode bases of varying width. Simulations demonstrate benefits for reducing self-heating and thermal power loss, which reduces overall on-state resistance and increases reverse break down voltages.

Power electronic and optoelectronic devices with interdigitated electrodes

A fully integrated DC-DC converter utilizes digitally controlled dual output stages to achieve fast load transient recovery is presented. The DC-DC converter includes a main converter output stage connected in parallel with an auxiliary output stage. The main output stage is responsible for steady-state operation and is designed to achieve high conversion efficiency using large inductor and power transistors with low on-resistance. The auxiliary stage is responsible for transient suppression and is only active when a load transient occurs. The auxiliary output stage performs well with inductor and power transistors much smaller than those of the main switching stage and thus achieves well balanced power conversion efficiency and dynamic performance with a much smaller area penalty than previously described dual-output-stage converters.

Digitally controlled integrated DC-DC converter with transient suppression

An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (C) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and standard CMOS components on the same substrate. Reduced surface field (RESURF) technology is employed to optimize tradeoffs between high breakdown voltage and specific on-resistance. Device fabrication steps are compatible with standard CMOS flow and process modules can be added or removed from baseline CMOS technology.

High speed orthogonal gate EDMOS device and fabrication

A digital Class-D amplifier distortion suppression circuit design is disclosed. A distortion suppression feedback loop is described to improve audio performance by suppressing output stage non-linearity and improving power supply noise rejection achieving reduced THD+N. The feedback loop is placed around the power stage. It forces tracking between the audio band signals at the input and output of the power stage by automatically adjusting the gating signal timing based on sensed effective duty ratio error. Error sensing and compensation are performed using techniques that lend to simple circuit implementation.

Distortion suppression circuit for digital class-D audio amplifier

A spread spectrum system having a self-oscillating delay-line digital pulse width modulator and a method for mitigating electromagnetic interference. The spread spectrum system has a pseudo-random pattern generator connected to a digital-to-analog converter, which in turn is connected to a linear regulator. The linear regulator receives a reference voltage from the digital-to-analog converter and creates a frequency varying voltage that serves as an input voltage for delay elements of a delay-line based digital pulse width modulator. In response to frequency varying input signal, the delay-line based digital pulse width modulator generates a frequency varying voltage that is input to a switching network to vary its switching frequency.

Circuit and method for reducing electromagnetic interference

Method of fabricating a fast programmable flash E.sup.2 PROM cell

A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed. Other devices, systems and methods are also disclosed.

Windowed source and segmented backgate contact linear geometry source

Windowed and segmented linear geometry source cell for power DMOS

A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

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Thornhill, Canada

Wai Tung Ng