Altera Corporation

Wai Tat Wong

Dinesh D Patil

Chuan Thim Khor

Edwin Yew Fatt Kok

Wilfred Wee Kee King

Tee Wee Tan

Kok Hong Chan

Ting Lok Song

In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.

Integrated circuit calibration system using general purpose processors

The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Dynamic clock-data phase alignment in a source synchronous interface circuit

One embodiment relates to a method of calibrating duty cycle distortion. A data rate of a physical layer interface is changed from a lower rate to a higher rate, and a data rate of one or more transceivers associated with the physical layer interface is changed from the lower rate to the higher rate. An electrical idle state is maintained after changing the data rate of the transceiver. Duty cycle distortion calibration for one or more transceivers associated with the physical layer interface is then performed during the electrical idle state. Other embodiments and features are also disclosed.

Method and apparatus to calibrate duty cycle distortion

Methods, circuits, and apparatus for correcting the phase of a clock signal are presented. In one method, an operation is included for receiving, from a plurality of input lines, a plurality of input clock signals with respective input clock phases. The input clock phases form an ordered sequence of clock phases. The method further includes an operation for transmitting, over a plurality of output lines, a plurality of output clock signals with respective output clock phases. The input and output lines are coupled to a serially coupled ring of resistors, where each resistor in the ring has a terminal coupled to an input line and the other terminal coupled to an output line. Further, each output clock phase has a value that is between successive input clock phases of the ordered sequence of clock phases.

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Bukit Mertajam, Malaysia

Wai Tat Wong