Texas Instruments Corporation

Wai Lee

Erika Lynn Mazotti

Sreenivasan Kalyani Koduri

Ricky A Jackson

Steven Alfred Kummerl

Dok Won Lee

John William Fattaruso

Toshiyuki Sakuta

Leslie Edward Stark

Keith Eric Sanborn

Paul Eric Landman

Steve Edward Harrell

Baher S Haroun

Mark R Visokay

Srinath Mathur Ramaswamy

William David French

Lei Ding

Steven Loveless

Michael De Wit

An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.

Resistor with exponential-weighted trim

In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

Film covers for sensor packages

Monolithic humidity sensor devices, and methods of manufacture. The devices include circuitry on or over a silicon substrate. A primary passivation barrier is formed over the circuitry with conductive vias therethrough; a capacitor, comprising metal fingers with spaces therebetween, is formed above said primary passivation barrier and electrically coupled by the conductive vias to the circuitry. A secondary passivation barrier is formed over the capacitor. A hygroscopic material layer is formed over the secondary passivation barrier, wherein the capacitor is operable to exhibit a capacitance value responsive to moisture present in the hygroscopic material layer and the circuitry is operable to generate a signal responsive to said capacitance value.

Monolithic humidity sensor devices and methods of manufacture

In a described example, a circuit includes a sensor circuit including multiple magnetic field sensors having respective sensor outputs. The magnetic field sensors are configured to provide magnetic field sensor signals at the respective sensor outputs representative of a measure of current flow through a conductive structure. A combiner interface has combiner inputs and a combiner output. The combiner inputs are coupled to the respective sensor outputs. The combiner interface is configured to provide an aggregate sensor measurement at the combiner output responsive to the magnetic field sensor signals, in which the aggregate sensor measurement is decoupled from magnetic fields generated responsive to the current flow through the conductive structure.

Magnetic current sensing

Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.

Trimmable silicon-based thermistor with reduced stress dependence

A digitally-controlled oscillator (DCO) (), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO () is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (). Each of capacitors () has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger () that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic () that inverts the common node of the capacitors (). The switching time at the input of Schmitt trigger () depends upon the variable load presented by the array of switched capacitors (), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (). A digital phase-locked loop (PLL) clock generator circuit () including a phase detector (), digital loop filter () in combination with the DCO (), and a programmable frequency divider () providing a feedback path from the output of the DCO () to the phase detector (), is also disclosed. The PLL clock generator () may be used in an integrated circuit such as a digital signal processor () or microprocessor, and is particularly well-suited for use in a battery-powered portable electronic system ().

Digitally-controlled oscillator with switched-capacitor frequency selection

A digital multiplier for multiplying a plurality of multiplicand signals X -X representing a multiplicand and a plurality of multiplier signals Y -Y representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.

Low power multiplier

A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60). A digital phase-locked loop (PLL) clock generator circuit (50) including a phase detector (64), digital loop filter (62) in combination with the DCO (60), and a programmable frequency divider (66) providing a feedback path from the output of the DCO (60) to the phase detector (64), is also disclosed. The PLL clock generator (50) may be used in an integrated circuit such as a digital signal processor (30) or microprocessor, and is particularly well-suited for use in a battery-powered portable electronic system (200).

Digitally-controlled oscillator with switched-capacitor frequency

A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements 70 are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.

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Dallas, TX, United States of America

Wai Lee