Cirrus Logic Inc.

Avnera Corporation

Asp Technologies

Other

Prophesi Technologies, Inc.

Wai Laing Lee

Lei Wang

Garry Link

Jianping Wen

Axel Thomsen

Dan Bernard Kasha

Edwin De Angel

Chung-Kai Chow

Joel W Page

Hong Helena Zheng

Eric J Swanson

Douglas S Piasecki

Karl Ernesto Thompson

Carlos Esteban Mu&ntilde;oz

Amit Kumar

Patrick A Quinn

Xudong Zhao

Eric T King

Ali Hadiashar

Kelly Michael Mekechuk

Alexander C Stange

Garry N Link

Shawn Stapleton

Carlos Estaban Mu&ntilde;oz

Adam C Broun

An amplifier for headphones including a current digital-to-analog converter (DAC) configured to output a current based on a digital audio input signal, an output electrically connected to a speaker and configured to output an output signal to the speaker, and a pulse width modulation (PWM) loop configured to receive an error signal, the error signal based on a difference between the current from the current DAC and a current of the output signal, and generate the output signal based on the error signal. The PWM loop includes an analog-to-digital converter (ADC) configured to receive an analog signal based on the current from the current DAC and output a digital signal representing the analog signal, and an encoder configured to receive the digital signal and output a pulse having a width based on the analog signal.

Digital-to-analog converter and amplifier for headphones

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vand the digital output port.

Digitally calibrated successive approximation register analog-to-digital converter

A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.

On-chip resistor divider compensation with a 2VRMS input

The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

Hybrid flash architecture of successive approximation register analog to digital converter

A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

Power supply for class G amplifier

The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

Programmable trim filter for successive approximation register analog to digital converter comparator

The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

Chopper stabilized comparator for successive approximation register analog to digital converter

The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

Reference disturbance mitigation in successive approximation register analog to digital converter

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vand the digital output port.

A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.

Low supply active current mirror

An adaptive noise canceling system can include a noise cancellation processor having an audio input for receiving an input audio signal, a microphone input structured to receive one or more microphone signals from a monitored environment, and a filter processor structured to produce a filtering function based on one or more filter parameters. The system can also include an adaptivity processor structured to change the one or more filter parameters in the noise cancellation processor based on a changing operating environment of the adaptive noise canceling system.

Noise cancellation system

A circuit can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V, wherein each top plate is also switchably electrically coupled with a common mode voltage V, and wherein each bottom plate is switchably electrically coupled between a first input voltage V, a reference voltage V, the common mode voltage V, and ground; a second plurality of capacitors C[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V, wherein each top plate is also switchably electrically coupled with the common mode voltage V, and wherein each bottom plate is switchably electrically coupled between a second input voltage V, the reference voltage V, the common mode voltage V, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V.

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Austin, TX, United States of America

Wai Laing Lee