Taiwan Semiconductor Manufacturing Comp. Ltd.

Synopsys, Inc.

Springsoft, Inc.

Synopsys Taiwan Co., Ltd.

Springsoft Usa, Inc.

Wai-Kei Mak

Sheng-Hsiung Chen

Ting-Chi Wang

Ren-Song Tsay

Fong-Yuan Chang

Meng-Kai Hsu

Tung-Chieh Chen

Yu-Hsiang Cheng

Ding-Wei Huang

Sheng-hsiung Chen

Hsuan-Han Liang

Fong-yuan Chang

Kuan-Yu Chen

Tsu-Ling Hsiung

Bo-Yang Chen

Chi-Chun Fang

Hsiu-Chu Hsu

The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout, wherein the first layout includes a first row and a second row adjacent to the first row; (b) dividing the first layout into a plurality of regions; (c) calculating a first density of each of the plurality of regions; (d) calculating, for a first region of the plurality of regions, a first probability of altering cell versions for cells in the first region according to the first density of the first region; (e) altering cell versions of one or more cells in the first region according to a comparison between the first probability and a first threshold; and (f) rearranging the cells in the first layout to reduce cell overlap.

Method, non-transitory computer-readable medium, and apparatus for arranging electrical components within a semiconductor device

The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.

Method and system of generating a layout diagram

A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

Method and system of revising a layout diagram

A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout includes a plurality of patterns in one or more layers of the layout; performing a coloring operation; forming a list comprising at least one uncolorable cell group (UCG) of the layout based on a result of the coloring operation, where each of the at least one UCG comprises at least one uncolorable cell; and performing a first refinement for each UCG on the list. The first refinement is performed through: performing a movement on at least one uncolorable cell of the UCG; determining whether the UCG is colorable; and refining the layout by accepting the movement and removing the UCG from the list in response to the UCG being determined to be colorable.

Method, system, and storage medium for resolving coloring conflict in multi-patterning lithography

A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.

Separation and minimum wire length constrained maze routing method and system

A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ratio for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.

Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratios

A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the 'H/V Demand Ratio.' From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio

A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero.

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Hsinchu, Taiwan

Wai-Kei Mak