California Institute of Technology

The United States of America As Represented by the Administrator of the

Wai-Chi Fang

Bing J Sheu

Timothy J Shaw

Jeffrey W Yu

Chi-Yung Chang

Jaw-Chyng Lue

Michael A Newell

John C Curlander

Leon Alkalaj

William T Johnson

A system with applications in pattern recognition, or classification, of DNA assay samples. Because DNA reference and sample material in wells of an assay may be caused to fluoresce depending upon dye added to the material, the resulting light may be imaged onto an embodiment comprising an array of photodetectors and an adaptive neural network, with applications to DNA analysis. Other embodiments are described and claimed.

Biochip microsystem for bioinformatics recognition and analysis

A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

Electronic processing and control system with programmable hardware

The invention is embodied in an image data system including a lossy image compressor having an image compression ratio in excess of 10 for producing first compressed image data from an original image, the first compressed image data specifying a corresponding one of a set of predetermined images, apparatus for computing an difference between the original image and the predetermined image specified by the first compressed image data and a lossless image compressor for compressing at least the difference to produce second compressed image data.

Data compression neural network with winner-take-all function

The array processor includes a grid of individual morphological processing elements formed on a VLSI chip. Each element of the grid includes a photo-detector for directly sensing a pixel of an image projected upon the chip. A signal generated by the photo-detector is sensed by a threshold circuit which outputs a binary value having a value depending upon the intensity of the light detector by the photo-detector. Each element also includes morphological processing circuitry for manipulating the binary value received from the threshold detector in accordance with predetermined morphological processing operations and in accordance with binary values received from adjacent processing elements. After modification of the binary value by application of one or more morphological processing operations, the binary value of each processing element is used to control a respective LCD element for displaying a pixel of a modified image. In this manner, all pixels of a modified image are output in parallel. By implementing the photo-detector, morphological processing circuitry and LCD output all on a VLSI chip, the array processor is capable is achieving real-time processing of two-dimensional images. An embodiment is also described wherein electrical output, rather than an LCD output, is provided.

Array processor for morphological image processing

The present invention is a block adaptive quantizer and an associated VLSI processor to provide real-time data compression for high resolution imaging radar systems. The block adaptive quantizer receives data from a synthetic radar aperture in a burst-mode. The block adaptive quantizer encodes and quantizes the data via a data-compression scheme. The image data is encoded by the block adaptive quantizer using thresholds generated from current bursts of image data collected.

VLSI processor design of real-time data compression for high resolution

A motion video data system includes a compression system, including an image compressor, an image decompressor correlative to the image compressor having an input connected to an output of the image compressor, a feedback summing node having one input connected to an output of the image decompressor, a picture memory having an input connected to an output of the feedback summing node, apparatus for comparing an image stored in the picture memory with a received input image and deducing therefrom pixels having differences between the stored image and the received image and for retrieving from the picture memory a partial image including the pixels only and applying the partial image to another input of the feedback summing node, whereby to produce at the output of the feedback summing node an updated decompressed image, a subtraction node having one input connected to received the received image and another input connected to receive the partial image so as to generate a difference image, the image compressor having an input connected to receive the difference image whereby to produce a compressed difference image at the output of the image compressor.

Motion video compression system with neural network having

A system for data compression utilizing systolic array architecture for Vector Quantization (VQ) is disclosed for both full-searched and tree-searched. For a tree-searched VQ, the special case of a Binary Tree-Search VQ (BTSVQ) is disclosed with identical Processing Elements (PE) in the array for both a Raw-Codebook VQ (RCVQ) and a Difference-Codebook VQ (DCVQ) algorithm. A fault tolerant system is disclosed which allows a PE that has developed a fault to be bypassed in the array and replaced by a spare at the end of the array, with codebook memory assignment shifted one PE past the faulty PE of the array.

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San Marino, CA, United States of America

Wai-Chi Fang