Adeia Semiconductor Bonding Technologies Inc.

Google Inc.

Invensas LLC

Wael Zohni

Belgacem Haba

Richard Dewitt Crisp

Frank Lambrecht

Ilyas Mohammed

Zhuowen Sun

Ashok S Prabhu

Reynaldo Co

Willmar E Subido

Min Tao

Abiola A Awujoola

Hoki Kim

Rizza Lee Saga Cizek

Yong Qin Chen

Ellis Chau

William P Schmidt

Philip R Osborn

Jeremy Plunkett

Rajesh Katkar

Michael John Sebastian Smith

Philip Damberg

Akash Agrawal

Liang Wang

Craig S Mitchell

Masud Beroz

Kyong-Mo Bang

David A Gibson

Yoichi Kubota

Jesse B Thompson

Stuart E Wilson

Young-Gon Kim

Grant Villavicencio

Ronald Patrick Green

L Elliott Pflughaupt

Chung-Chuan Tseng

Cyprian Emeka Uzoh

Joseph Charles Fjelstad

Javier A DeLaCruz

Suresh Rajan

Charles Gerard Woychik

David T Wang

Guilian Gao

Kishor V Desai

Philip Arnold Ferolito

Daniel L Rosenband

Michael J S Smith

Jeremy Werner

Christopher Lattin

Javier A Delacruz

Simon McElrea

Hoang Nguyen

Marjorie Cara

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Wire bond wires for interference shielding

In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.

Pressing of wire bond wire tips to provide bent-over tips

A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

Bonding of laminates with electrical interconnects

A microelectronic assembly () or system () includes at least one microelectronic package () having a microelectronic element () mounted face up above a first surface () of a substrate (), one or more columns () of contacts () extending in a first direction () along the microelectronic element front face. Columns (A,B,A,B) of terminals () exposed at a second surface () of the substrate extend in the first direction. First terminals () exposed at surface () in a central region () thereof having width () not more than three and one-half times a minimum pitch () of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows

A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows

A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

Stacked chip-on-board module with edge connector

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

Embedded wire bond wires

Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.

Dies-on-package devices and methods therefor

A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. A microelectronic element may be attached and electrically connected with conductive features at the second surface, and a dielectric encapsulation can be formed contacting the second surface and surfaces of the microelectronic element. Electrically conductive features at the interconnection surface can be configured for connection with corresponding features of a first external component, and the electrical connectors can be configured for connection with corresponding features of a second external component.

Microelectronic assembly with redistribution structure formed on carrier

Growing community of inventors

San Jose, CA, United States of America

Wael Zohni