Advanced Micro Devices Corporation

Wade L Williams

Philip Enrique Madrid

John Phillip Hansen

Ronald W Stence

Melanie D Typaldos

Eric G Chambers

Robert Paul Gittinger

A device and method for transferring data is disclosed that facilitates data transfers between devices having different clock domains. The data transfer from one device to another occurs through a First In First Out memory (FIFO). The relative number of FIFO access cycles to the FIFO is controlled to maintain a desired FIFO fullness. Setting the desired FIFO fullness to a desired value allows control of data transfer latency between devices.

Device and method for transferring data between devices

A peripheral device selected with a chip select is mapped onto address space occupied by DRAM without causing internal or external contentions. A first address range is provided for accessing DRAM. A second address range is provided for accessing another device. The second address range is within the first address range. A row address strobe is provided for accesses within both the first and second address ranges but the column address strobe to the DRAM is inhibited when a memory access occurs within the second address range.

Overlapping peripheral chip select space with DRAM on a microcontroller with an integrated DRAM controller

A microcontroller integrates an internal memory accessible by the cores included thereon. Logic within the microcontroller compares memory addresses generated by the cores to values in a configuration register specifying a memory address range in which the internal memory resides. The logic generates a chip select signal to the internal memory if the memory address generated resides within the specified address range to enable accesses by the cores to the internal memory. The integrated circuit may be configured in a debug mode wherein the chip select signal is inhibited to the internal memory, however the chip select signal is provided external to the integrated circuit on a pin. The chip select signal may then be used to select an external memory which serves to overlay the internal memory address range. Thus the debug mode allows instruction code and data to reside in the external memory rather than the internal memory while in the debug mode. This facilitates debugging of the code since the contents of the external memory may be examined, for example by an in-circuit emulator, in a less intrusive manner than the contents of the internal memory may be examined. The debug mode may be enabled by asserting a signal upon a predefined pin at the conclusion of reset of the microcontroller. By providing the predefined pin for placing the microcontroller into the debug mode, the microcontroller may be placed into the debug mode for debug purposes without changing the instruction code being executed thereon. Furthermore, the in-circuit emulator need not have knowledge of the internal memory address range.

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Austin, TX, United States of America

Wade L Williams