Hughes Aircraft Company

Wade J Stone

Edwin A Kelley

Kikuo Ichiroku

Don C Devendorf

Howard S Nussbaum

William P Posey

Benjamin Felder

A linear predictive ADC employs a fully feed forward design to extend its dynamic range, allow greater speed of operation, achieve stable operation and eliminate a requirement for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a subsequent value of the input signal. After conversion back to analog format, the predicted signal is compared with the actual subsequent value of the input signal to produce an error signal that is converted to a digital format by a second quantizer (Qf). The digital predicted signal is fed forward and combined with the digital error signal to produce a high precision digital output. The analog error signal is preferably amplified prior to digitation to take advantage of the full bit capacity of the second quanitzer (Qf), and then digitally de-amplified back to its original scale. Digital gain and offset adjustment mechanisms (44, 50) are preferably provided to compensate for amplification/de-amplification mismatches and system offsets. The quantizers (Qc, Qf), predictor (32) and a digital register (36) that interfaces between the predictor and the output combiner (46) are clocked in a set sequence to ensure that the predicted signal from the register (36) corresponds in time to the error signal presented to the output combiner (46).

Feed forward predictive analog-to-digital converter

A digital radio frequency (RF) or intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals contained in a predetermined FDM band including an RF amplifier, an RF bandpass anti-alias filter, and an analog-to-digital (A/D) converter. The sample frequency F.sub.s of the A/D converter is lower than the lowest frequency in the predetermined FDM band and is selected to meet certain specified conditions based on the passband and stop band edges of the anti-alias filter so that the output of the A/D converter contains a non-distorted aliased frequency down converted digital version of the predetermined FDM band which is located between 0 Hz and one-half the sampling frequency. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC). Digital low pass filtering isolates the desired channel centered at DC, and a digital complex mixer can be used to translate the isolated selected channel to a predetermined IF frequency. The in-phase portion of the digital IF centered selected channel or the DC centered complex envelope selected channel can then be provided to appropriate demodulation or decoder networks.

Efficient digital frequency division multiplexed signal receiver

An automatically gain controlled multiple approximation analog to digital converter including a gain controlled amplifier responsive to the difference between an analog input signal and an analog version of a digital approximation of the analog input signal for providing a gain controlled analog residue signal, a quantizer for converting the gain controlled analog residue signal to a gain controlled digital residue signal, a digital divide circuit for dividing the gain controlled digital residue signal by a factor representative of the gain contained therein to provide a restored digital residue signal representative of the analog residue signal before it was amplified by the gain controlled amplifier, and a summing circuit for adding the restored digital residue signal and the digital approximation to provide the output of the gain controlled analog to digital converter. The gain controlled amplifier and the divide circuit are controlled by a gain control circuit that tends to maintain the output of the quantizer between first and second thresholds. Circuitry for providing the digital approximation of the analog input signal can include a linear predictor, or a sample and hold circuit and a coarse quantizer, for example.

Low cost AGC function for multiple approximation A/D converters

The efficient high-speed N word comparator receives a plurality of digital inputs which are simultaneously compared by conducting a digital to analog conversion on each input signal and comparing the analog signals in a plurality of weighted analog comparators. Each comparator conducts a balance between an associated input signal and the remaining input signals providing an output indication if the associated signal is an extremum value. The outputs of the comparators are then encoded to provide an address of the digital input of the extremum value and to select the input value through a multiplexer. The address and the value are then provided to subsequent circuitry for processing. Simultaneous comparison of all signals provides significantly reduced ripple delay while reducing the requirements for hardware allowing monolithic implementation for a larger plurality of inputs.

Efficient high speed N-word comparator

A digital intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals including analog circuitry for receiving FDM signals and an analog-to-digital (A/D) converter for converting the received signals to a sampled digital received signal. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC). Digital low pass filtering isolates the desired channel centered at DC, and a digital complex mixer can be used to translate the isolated selected channel to a predetermined IF frequency. The in-phase portion of the digital IF centered selected channel or the DC centered complex envelope selected channel can then be provided to appropriate demodulation or decoder networks.

According to the invention, a high-speed digital data communication system employs current mode circuitry as input and output devices at the ends of a transmission line, such as the interconnections between integrated circuit chips. Specifically, a current mode driver switch generates output current amplitudes responsive to a source of a digital signal representative of data to be transmitted. The switch output is connected to the input of a transmission line. The output of the transmission line is connected to the input of a receiving circuit that responds to the current amplitudes and has an input at an approximately constant voltage level. The receiving circuit is a transistor connected in a common base configuration. The emitter of the transistor is connected to the output of the transmission line. The base of the transistor is connected to a constant voltage source. A pulse shaper in the form of a Schmitt trigger has positive feedback from output to input. The described current mode circuitry is incorporated into an integrated circuit chip.

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Los Angeles, CA, United States of America

Wade J Stone