Dell Products Inc.

Wade Andrew Butcher

Timothy Michael Lambert

Elie Antoun Jreij

Hendrich M Hernandez

Stuart Allen Berke

Lee Eric Ballard

Vijay Bharat Nijhawan

Vadhiraj Sankaranarayanan

Sandor Tibor Farkas

Sumanth Vidyadhara

John Erven Jenne

Mark A Muccini

Jonathan Foster Lewis

Richard L Holmberg

Brian L Brelsford

Bhyrav M Mutnury

Rama Rao Bisa

Chitrak Gupta

Shawn Joel Dube

Deepaganesh Paulraj

Raveendra Babu Madala

Yogesh Prabhakar Kulkarni

Akkiah Choudary Maddukuri

Johan Rahardjo

Jordan Chin

Sushma Basavarajaiah

Kevin Allen Hughes

Arulnambi Raju

Kurtis John Bowman

Terry Wayne Liles

Philip John Brisky

Joseph Danny King

Wayne Kenneth Cook

William A Moyes

Raghavendra Venkataramudu

Richard Louis Holmberg, Jr

Yayun Liu

Rich M Hernandez

Jonathan Leonard Deonarine

Dinesh K Ragupathi

A method for provisioning swap spaces. The method includes: receiving, from a platform orchestrator of a service delivery platform and directed to provisioning a swap space, a swap space instruction specifying a swap space owner and a swap space size; requesting, from the platform orchestrator in response to receiving the swap space instruction and subsequently receiving, a swap space configuration associated with the swap space; based on at least a portion of the swap space configuration: selecting, at least based on the swap space size, at least one physical memory device; creating at least one volume on the at least one physical memory device; creating an emulated memory drive using the at least one volume; and presenting, to the swap space owner, the emulated memory drive as attached swap space representing the swap space.

On-demand swap space for various platform components

An information handling system may include at least one processor; and an information handling resource, wherein the information handling resource has hardware definition information associated therewith, and wherein the hardware definition information is not stored in a physical storage resource of the information handling resource; wherein the information handling system is configured to: determine a storage location of a database including the hardware definition information of the information handling resource; and retrieve the hardware definition information from the database.

Software-defined FRU

An information handling system includes first and second lines of a differential pair. A baseboard management controller (BMC) periodically determines a resistance of the first line and a resistance of the second line. If the first resistance is substantially equal to the second resistance, then the BMC provides a corrosion signal to a remote diagnostic system.

System and method for sensing corrosion in an enclosure of an information handling system

An information handling system includes a power supply and a baseboard management controller (BMC). The power supply includes an input power monitor module and a communication interface. The input power monitor module is configured to detect a total harmonic distortion (THD) on a power input to the power supply, to determine that the THD is greater than a THD threshold, and to provide an indication that the THD is greater than the THD threshold on the communication interface. The BMC is coupled to the communication interface, and is configured to receive the first indication and to enter an item into a log of the information handling system in response to receiving the indication.

System and method for using input power line telemetry in an information handling system

In accordance with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a failure analysis module comprising a program of instructions, the failure analysis module configured to, when read and executed by the processor, set a predictive failure threshold for each of the plurality of non-volatile memories based at least on functional parameters of such non-volatile memory, and adapt the predictive failure threshold for each of the plurality of non-volatile memories based at least on health status parameters of such non-volatile memory.

Systems and methods for adaptive proactive failure analysis for memories

In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces.

System and method of rerouting an inter-processor communication link based on a link utilization value

An information handling system includes a current detector module and a baseboard management controller (BMC). The current detector module is configured to detect current slew-rate for an element of the information handling system, to determine that the current slew-rate is greater than a current slew-rate threshold, and to provide an indication that the current slew-rate is greater than the current slew-rate threshold on a communication interface. The BMC may enter an item into a log of the information handling system in response to receiving an indication.

System and method for using current slew-rate telemetry in an information handling system

In one or more embodiments, an information handling system (IHS) may receive, from another IHS via a first network, a dynamic host configuration protocol discovery request, provide, via the first network, a first Internet protocol version four (IPv4) address to the other IHS, and associate a first Internet protocol version six (IPv6) address. The IHS may receive a domain name service (DNS) lookup request from the first information handling system, provide a multicast DNS (mDNS) request, based at least on logical name information from the DNS lookup request, to a second network, and receive a mDNS response that includes a second IPv6 address associated with the logical name information from the DNS lookup request. In response to receiving the mDNS response, the IHS may configure at least one network address translation configuration that associates that associates the second IPv6 address and a second IPv4 address.

System and method of utilizing multiple networks

An Information Handling System (IHS) has persistent memory device(s) coupled to a processor. Each memory device includes a first firmware image, version identifying information associated with the first firmware image, and device type identifying information. A firmware interface suite coupled to the processor has a firmware interface that is executed by the processor. The processor responds to identifying a trigger condition for automatic intra-system firmware update of a persistent memory device. The processor accesses the version identifying information and the device type identifying information for a first memory device containing the first firmware image of the persistent memory device(s). The processor associates the device type identifying information with device type information for a second memory device. In response to the first firmware image being different from the second firmware image, the processor selectively replaces the first firmware image on the first memory device with the second firmware image.

Automated intra-system persistent memory updates

A system includes servers that are connected in series, and a top of rack (TOR) switch having a first TOR switch port and a second TOR switch port that are connected to a first end and a second end, respectively, of the series connected servers. A multi chassis link aggregation group may be established on the first TOR switch port and the second TOR switch port to transform the series connected servers into a single logical channel. A highest media access control address is determined from the servers to represent the single logical channel.

System and method for port reduction using multiple chassis link aggregation group for stacked devices

An information handling system includes a processor and memory devices that each include a voltage regulator configured to be enabled by a command from the processor. The processor boots the information handling system, including providing the command to the memory devices, and detects that one of the memory devices failed to boot. The processor determines that it is unknown whether the failing memory device is the first memory device or the second memory device. In response, the processor determines which one of the memory devices failed to boot, by rebooting the information handling system, providing a command to a selected one of the memory devices, and determining whether or not the selected one of the memory devices failed to boot.

System and method for determining DIMM failures using on-DIMM voltage regulators

In one or more embodiments, a device may include and/or implement a physical function and multiple virtual functions that are operable to be arranged in a logical nested hierarchy and operable to be configured to respective virtual machines in a hierarchy of nested virtual machines. For example, the physical function may be configured to receive a request, issued from a virtual function of the multiple virtual functions corresponding to a Nth level of nesting of the multiple virtual functions. Until a response to the request is received, the physical function may iteratively provide the request to a virtual function of the multiple virtual functions corresponding to a current level of nesting and if the response to the request is not received from the virtual function corresponding to the current level of nesting, utilize the current level of nesting as a level immediately below the current level of nesting.

Hierarchically nested virtualized functions having a physical function providing processing requests and responses to each level of the hierarchy

A differential pair group equalization system includes a board providing a differential trace pair group with a plurality of differential trace pairs, each of a transmitter device and a receiver device are coupled to the board and the differential trace pairs in the differential trace pair group. At least one of the transmitter device and the receiver device operates to identify a first differential trace pair in the differential trace pair group, and adjust second differential trace pair equalization parameters for a second differential trace pair in the differential trace pair group. If it is determined that first differential trace pair signal transmission capabilities for the first differential trace pair have improved in response to the adjustment of the second differential trace pair equalization parameters for the second differential trace pair the second differential trace pair equalization parameters are set for the second differential trace pair.

Differential pair group equalization system

A method, an information handling system (IHS), an IHS and a network interface system for transmitting data in an IHS. The method includes detecting, via a network interface device controller of a first IHS, a first memory transaction request from a second IHS to a first system memory of the first IHS. A plurality of first data associated with the first memory transaction request is received. A first peer to peer message is transmitted to a hardware logic device (HLD). The first peer to peer message includes a first action for the HLD. The HLD is triggered to process the first data according to the first action such that the HLD generates a plurality of second data.

Growing community of inventors

Cedar Park, TX, United States of America

Wade Andrew Butcher