Aurora Systems, Inc.

Akamba Corporation

W Spencer Worley, Iii

William Thomas Weatherford

John A Vastano

Eoin B MacDonell

Jack J Smith

Richard T Burright

Edwin Lyle Hudson

Wing Hong Chow

Raymond Pinkham

John Gray Campbell

An adapter card for managing connections between clients and a network server off-loads the connection management burden from the server. The adapter card includes a memory with an embedded proxy application and a communication protocol stack, a processing unit for executing the application code, a network controller for interfacing with an internetwork, and a bus protocol bridge for interfacing with the internal bus of the network server. The proxy application receives client requests on behalf of the server over relatively slow and unreliable network connections, and submits the requests to the server over fast, reliable bus connections.

System and method for managing connections between a client and a server

An adapter card for managing connections between clients and a network server off-loads the connection management burden from the server. The adapter card includes a memory with an embedded proxy application and a communication protocol stack, a processing unit for executing the application code, a network controller for interfacing with an internetwork, and a bus protocol bridge for interfacing with the internal bus of the network server. The proxy application receives client requests on behalf of the server over relatively slow and unreliable network connections, and submits the requests to the server over fast, reliable bus connections. A proxy cache provides storage for server responses, so that the proxy application can provide the stored responses to clients without re-accessing the server. Buffers are allocated to a particular client connection only after it is determined that data will be exchanged between the server and the client.

Network adaptor card with reverse proxy and cache and method implemented therewith

A system and method for asserting compound data words on a display pixel according to a field sequential driving scheme is disclosed. In a particular embodiment, a display driver circuit includes an output controller for generating control signals to sequentially assert a first portion of a first compound data word on the display pixel, assert a first portion of a second compound data word on the display pixel, assert a second portion of the first compound data on the display pixel, and assert a second portion of the second compound data word on the display pixel. A particular display driver circuit includes a compound data generator which generates the compound data words from data words of a first type. The first portions of the compound data words are generated from the first type data words according to one predefined mapping scheme, and the second portions are generated according to another predefined mapping scheme.

System and method for using compound data words in a field sequential display driving scheme

An adapter card for managing connections between clients and a network server off-loads the connection management burden from the server. The adapter card includes a memory with an embedded proxy application and a communication protocol stack, a processing unit for executing the application code, a network controller for interfacing with an internetwork, and a bus protocol bridge for interfacing with the internal bus of the network server. The proxy application receives client requests on behalf of the server over relatively slow and unreliable network connections, and submits the requests to the server over fast, reliable bus connections. Buffers are allocated to a particular client connection only after it is determined that data will be exchanged between the server and the client.

System and method for managing connections between clients and a server with independent connection and data buffers

A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.

System and method for reducing peak current and bandwidth requirements in a display driver circuit

A system and method for reducing the phase difference between adjacent gray scale values employ compound data words. The compound data words include a first group of data bits and a second group of data bits. A display driver circuit is configured to provide display control signals causing each bit of the first group of data bits to be asserted on the display pixel for a coequal time period, and causing each bit of the second group of data bits to be asserted on the display pixel for a time period dependent on an associated significance of each bit. Optionally, the display driver circuit further includes a compound data generator configured to provide the compound data words. A method for asserting a compound data word on a display pixel includes the steps of asserting each bit of the first group of bits on the display pixel for a coequal time period, and asserting each bit of the second group of bits on the display pixel for a time period dependent on an associated significance of each bit.

System and method for using compound data words to reduce the data phase

A system and method for planarizing n-bit display data into m-bit data. The system includes a plurality of input terminals, a plurality of output terminals, and a first storage bank having a bit-depth less than m. In one embodiment, the first storage bank is a bi-directional shift register including a clock input terminal, for receiving a data shift signal, and a direction terminal for receiving a direction control signal. In a particular embodiment, the bi-directional shift register includes a plurality of flip-flops and a plurality of multiplexers, both arranged in a rectangular array of columns and rows. Optionally, the system includes a second storage bank, and data is shifted into one storage bank while data is being shifted out of the other storage bank.

System and method for data planarization

A display driver circuit and method for receiving a display data stream, modifying the display data stream to enhance gray scale performance, and outputting the modified display data stream. The display driver includes a forced state generator for adding at least one forced state to the display data stream to create the modified display data stream. The forced state generator includes a multiplexer and a forced state controller. The multiplexer includes a data input terminal for receiving the display data stream, a first forced state input terminal for receiving first forced state data, a second forced state input terminal for receiving second forced state data, a data output terminal for outputting the modified display data stream, and a pair of control input terminals. The forced state controller includes a pair of control output terminals coupled the control input terminals of the multiplexer. Responsive to signals asserted on the control input terminals, the multiplexer selectively couples its data input terminal, its first forced state input terminal, and its second forced state input terminal with its data output terminal, thus generating the modified display data stream.

Growing community of inventors

Half Moon Bay, CA, United States of America

W Spencer Worley, Iii