Mips Technologies, Inc.

Arm Finance Overseas Limited

Other

W Patrick Hays

Robert Gelinas

Sol Katzman

William James Dally

Staffan Ericsson

Sam Rosen

Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.

Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch

Executing an instruction of currently active thread before context switch upon receiving inactive context ID to be activated

Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities

Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register.

System and method for extracting fields from packets having fields spread over more than one register

Method for extracting fields from packets having fields spread over more than one register

Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source

A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low-overhead interrupts.

High performance RISC instruction set digital signal processor having circular buffer and looping controls

Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to send a separate request for the result. In accordance with the systems and methods, a bus controller generates a system bus operation that sends (to the device) a thread identifier and a data request formulated in one thread by a processor that context switches to a second thread.

Systems and methods for extending register addresses in compressed instruction sets are capable of executing extended register instructions that supplement the bits needed to address registers. The extended register instruction precedes corresponding standard instruction, and register the bits from the extend instruction are combined with register bits from the standard instruction to obtain a longer register address.

Growing community of inventors

Cambridge, MA, United States of America

W Patrick Hays