Advanced Micro Devices Corporation

Yield Dynamics, Inc.

W Jarrett Campbell

Stacy K Firth

Anthony John Toprac

Michael R Conboy

Michael Lee Miller

Jeremy Sam Lansford

Christopher H Raeder

Qingsu Wang

Terrence J Riley

Terri A Couteau

A system and method for estimating errors within a semiconductor fabrication process. The system identifies an optimal number of error components based upon relevant context items. The system further estimates the error within the fabrication process and attributes portions of the error to each of the identified error components based upon feedback data received from the manufacturing process.

System and method for estimating error in a manufacturing process

A system and method for controlling critical dimension in a semiconductor manufacturing process. The system controls critical dimension by altering focus and exposure settings, based on a single measured attribute (i.e., critical dimension) and on a process model equation. The system further systematically varies focus and exposure settings (e.g., by introducing variable deviation values), in order to provide unique and stable solutions for parameters within the process model equation.

System and method for controlling critical dimension in a semiconductor manufacturing process

A metbod for perforning a wafer-less qualification of a processing tool includes creating a wafer-less qualification model for the processing tool. Qualification data is generated from the processing tool iiiring a wafer-less qualification process. The qualification data is compared with the wafer-less qualification model. The processig tool is determined to be operating in a predefined state based on the comparison of the qualification data with the wafer-less qualification model.

Wafer-less qualification of a processing tool

A method for processing a semiconductor topography is presented. In the present processing method, a semiconductor topography may be provided having a polysilicon feature arranged above a semiconductor substrate. The polysilicon feature may have an initial polysilicon feature critical dimension (CD). A chemical mixture, preferably contained in a chemical vessel, may also be provided. A polysilicon etch rate-effective attribute of the chemical mixture may be measured. Subsequently, an exposure time to the chemical mixture for the semiconductor topography may be calculated from the polysilicon etch rate-effective attribute, the initial polysilicon feature CD, and a goal polysilicon feature CD. By calculating an exposure time for the semiconductor topography in such a manner, the method preferably allows a final polysilicon feature CD to be more accurately controlled than in conventional processes.

System and method for controlling polysilicon feature critical dimension during processing

A method of controlling surface non-uniformity of a process layer includes receiving a first lot of wafers, and polishing a process layer of the first lot of wafers. A control variable of the polishing operations is measured after the polishing is performed on the process layer. A first adjustment input for an arm oscillation length of a polishing tool is determined based on the measurement of the control variable. A process layer of a second lot of wafers is polished using the adjustment input for the arm oscillation length. A controller for controlling surface non-uniformity of a process layer includes an optimizer and an interface. The optimizer is adapted to determine a first adjustment input for arm oscillation length of a polishing tool based on a measurement of a control variable from a first lot of wafers. The interface is adapted to provide the first adjustment input to the polishing tool for polishing a second lot of wafers.

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Austin, TX, United States of America

W Jarrett Campbell