Vlsi Technology, Inc.

W Henry Potts

David R Evoy

Franklyn H Story

Joseph Alan Thomsen

Ned D Garinger

Brian N Fall

Kenneth P Caviasca

James B Nolan

Tein-Yow Yu

Deepak Verma

Pratiksh Parikh

Hrushikesh Nalubola

A digital computer system including a memory subsystem thereof for increasing the throughput of the digital computer system is disclosed, comprising a central processing unit (CPU), a main memory, and a Look-ahead Instruction Prefetch Buffer (LIPB) external to the CPU for prefetching at least one portion of instruction code from the main memory each time the CPU initiates a request for instruction code from the main memory and for accelerating the submission of the portion of instruction code to said CPU means upon request by said CPU means without a memory system delay that is usually required when accessing a larger number of memory locations in the main memory each time the CPU initiates an instruction code request. An intelligent posted write buffer (IPWB) is also provided for temporarily storing in a first-in first-out (FIFO) configuration a portion of write-to-memory data generated by the CPU executing a write operation and for subsequently applying the portion of write-to-memory data to the main memory thereby eliminating a possible stall incurred by the CPU while waiting for the write operation to be completed.

Memory subsystems having look-ahead instruction prefetch buffers and

A serial bus Input/Output (I/O) system has multiple I/O devices which are all connected in daisy-chain fashion on a serial bus. These I/O devices service peripherals that may generate different interrupt requests or DMA requests to the system controller. These requests are encoded, serialized and transmitted to the system controller on the serial bus, allowing the system controller to service a large number of interrupt requests and DMA requests via the serial bus with a very small number of external pins.

Serial bus I/O system and method for serializing interrupt requests and

A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount. A selector, for example, a multiplexor, selects output from either the first frequency divider or the second frequency divider as the system clock signal. When the first oscillating signal is being used to generate the system clock, the second input may be used to control the selection of frequency dividers.

Variable frequency clock for a computer system

Growing community of inventors

Tempe, AZ, United States of America

W Henry Potts