Motorola Corporation

W Eric Main

Michael McGinn

W David Pace

Dennis L Welty

Don W Zobel

Robert A Neidorff

Randall C Gray

Robert B Jarrett

David K Lovelace

Jeffrey C Durec

Gerald K Lunn

Roy H Espe

Jeffery C Durec

An RF buffer (10) supplies a single ended output signal and differential output signals. An average voltage of the differential output signals is compared to a reference voltage (VR) by an amplifier (40). The amplifier (40) provides a feedback signal for controlling the bias current conducted by a first transistor (24) and a mirrored bias current conducted by a second transistor (46). The bias currents conducted by the first and second transistors (24, 46) are used to generate the differential output signals (OUT-, OUT+) and are substantially independent of the signal level at an input terminal (20). The signal current conducted by the first transistor (24) controls an output transistor (66), while the signal current conducted by the second transistor (46) controls another output transistor (56) in the push-pull output stage of the RF buffer (10).

Circuit for RF buffer and method of operation

A amplifier (21) having increased linearity, low input impedance, and low noise is provided. The amplifier (21) has an input (22), a bias input, a first output (23), and a second output (33). A first transistor (26) has a collector coupled to the first output (23), a base coupled to the bias input, and an emitter. A first resistor (27) is coupled between the emitter of the first transistor (26) and the input (22). A second transistor (29) has a collector and base coupled in common, and an emitter coupled for receiving a power supply voltage. A second resistor (28) couples between the input (22) and the common base and collector of the second transistor (29). A third transistor (32) has a collector coupled to the second output (33), a base coupled to the common base and collector of the second transistor (29), and an emitter coupled for receiving the power supply voltage. An input signal applied to the input (22) generates a differential current at the first and second outputs (23, 33). The input signal and the differential current have a linear relationship.

Amplifier circuit having high linearity for cancelling third order

A demodulation circuit (10) performs quadrature demodulation on an IF input signal. The IF input signal processes through a preamplifier (12) to one input of a mixer (14). The mixer output goes to first and second multipliers (20, 22). A VCO (24) generates an oscillator signal that processes through a first multiplier (26) and first and second dividers (28, 30) to generate in-phase and quadrature recovered carrier signals that are applied to second inputs of the first and second multipliers which in turn produce the in-phase and quadrature demodulated baseband signals. A switching arrangement (32, 38, 40) for the multiplier and dividers provides the proper frequency signal to a second input of the mixer to generate sum and difference frequencies. A filter and amplifier at the output of the mixer removes the summation frequency leaving the difference frequency to the first and second multipliers.

Quadrature demodulator operable over different IF frequencies

A data slicer including a comparator and a clamping circuit has been provided wherein the clamping circuit functions to clamp a signal appearing at a first input of the comparator to a predetermined voltage swing. The first input of the comparator is coupled through a capacitive element to receive an input signal. The clamping circuit includes a first diode being coupled between the first input of the comparator and a first voltage. The clamping circuit also includes a transistor having its current carrying electrodes coupled between a first supply voltage terminal and the first input of the comparator. The control electrode of the transistor is coupled to receive a second voltage. The second input of the comparator is coupled to receive a bias voltage which is substantially equal to the midpoint of the first and second voltages. The data slicer further includes a hold circuit for disabling the clamping circuit.

Data slicer with hold

A variable gain control circuit comprising an input stage and an output stage is responsive to an applied input signal for providing an output signal. The input stage and output stage are independently biased by respective bias sources and each include circuitry responsive to a dynamic control voltage, the latter of which is generated in response to the input signal, to permit the absolute magnitudes of the input signal and output signal to exceed the respective bias sources. The ratio of the output and input signals is proportional to the ratio of the bias sources.

Class B variable gain control circuit

A circuit for producing output pulses in response to an alternating signal supplied to the input thereof which is comprised of a pair of complementary transistors cascoded between a pair of current mirror circuits which source and sink currents to and from a common terminal respectively. The alternating input signal is applied to the interconnected emitters of the two transistors thereby rendering one more conductive while the other is rendered less conductive and vice versa. The currents which are sourced or sunk at the common terminal are proportional to the currents flowing in the two transistors and are compared to cause an output transistor to switch operating states thereby producing the output pulse.

Data shaping circuit

An active differential load circuit which receives a differential input signal applied to first and second inputs thereof and produces a single ended output signal at an output thereof while unwanted higher frequency signals applied thereto are filtered from the output without ground currents. The load includes a pair of transistors which have, in the preferred embodiment, their collectors connected together via series connected first and second resistors with the interconnection between the two resistors being connected to the bases of the two transistors. The collectors are also respectively coupled to a pair of current sources and the respective emitters receiving the applied differential input signal. A filter capacitor is coupled between the collectors of the two transistors and efffectively shorts the unwanted higher frequency signals thereacross.

Balanced differential load and method

A variable reactance, the value of which is controllable, is produced between a pair of terminals of a variable reactance circuit comprising a pair of current steering circuits. First and second reactive components are coupled respectively between the pair of terminals and the first and second current steering circuits to produce first and second antiphase reactive currents'. The first reactive current is split by the first current steering circuit into first and second antiphased proportional currents. Likewise, the second reactive current is split by the second current steering circuit into third and fourth antiphased proportional currents with said first and third currents being antiphased with respect to each other. The first reactive current is summed at a first one of the pair of terminals with said first and third currents while the second reactive current is summed at the second one of the pair of terminals with said second and fourth currents to produce the variable reactance across the terminals.

Balanced variable reactance circuit and method of producing the same

A balanced LC oscillator for providing differential oscillator output signals includes a pair of transistors the emitters of which are connected to a voltage reference source that provides a fixed voltage thereto. The base electrodes of each transistor is cross coupled to the collector of the other transistor. The LC tank circuit is connected between the collectors of the two transistors and current supply is provided thereto. Although the potential at the bases of the two transistors vary with respect to the oscillator signal appearing thereat, the emitters are held at a fixed potential to eliminate any common mode signal that may otherwise be generated if the potential at the emitters was permitted to vary.

Balanced oscillator with constant emitter voltage level

A circuit for driving a serial data bus with serial logic data that is supplied to the circuit while buffering the logic data supplying circuit from the data bus. The circuit provides logic output pulses having controlled slew rates wherein the input logic data is not distorted but which inhibits undesired high frequency components associated with the fast rise and fall times of the leading and trailing edges of the input logic data pulses. The circuit comprises an inverting amplifier having capacitive feedback between the output and the inverting input of the amplifier, a buffer amplifier between the output of the inverting amplifier and the output of the circuit, and current switching circuitry for sinking and sourcing currents of equal magnitude at the input of the inverting amplifier depending on the relative magnitude of the input logic data pulses.

Fixed slew rate bus driver circuit

This relates to a circuit for clamping the voltage across first and second terminals (in this case the gate and source electrodes of a power MOSFET) in response to the receipt of a signal indicating a load fault. An input turnaround transistor receives the signal indicative of the fault and generates a current in response thereto which is applied to the base of a switching transistor. When this current exceeds a predetermined value, the switching transistor turns on which in turn causes a buffer circuit including a PNP transistor to turn on. When the buffer circuit turns on, current is drawn through a zener diode which is coupled to the second terminal. Thus, the clamping circuit between the gate and source terminals equals the voltage drop across the zener diode plus that dropped across the buffer circuit plus the saturation voltage of the switching transistor. Resistors are provided in the buffer circuit to provide for a certain amount of adjustment of the clamping voltage.

Clamp circuit

A reference capacitor is coupled in parallel with a capacitor of which the size thereof is variable and an oscillator is used to alternately charge and discharge both capacitors between first and second voltage levels. The absolute magnitude of the current flowing through the reference capacitor, which varies in proportion to the size of the variable capacitor, is detected which is indicative of the variations in size of the variable capacitor. If the variable capacitor is disposed in the fuel tank of a vehicle, water in the fuel will cause the effective capacitance value of the capacitor to increase which reduces the absolute magnitude of the current that is detected. The absolute magnitude of the detected current can be utilized to indicate excessive water levels in the fuel.

Water-in-fuel sensor circuit and method

A Class AB amplifier circuit includes bias circuitry for biasing the output transistor into partial conduction independent of the base-to-emitter voltage of the transistor. The bias circuitry is a simple circuit loop including the output transistor and forms the remainder of the amplifier circuit which can be fabricated in monolithic integrated circuit form. The loop comprises a differential amplifier for providing a substantially constant offset voltage across a pair of terminals between which is connected a current biasing component. The current biasing component is connected in series with the output transistor to produce a small quiescent current to flow therethrough, the value of which is independent of the transistor's characteristics.

Bias circuit which is independent of output device voltage

A balanced multiplier circuit for a subscriber loop interface circuit (SLIC) which provides both loop current to a two-wire bidirectional subscriber loop and suppression of longitudinal signals generated at the two-wire loop input to the SLIC while maintaining the midpoint load voltage at half the available power supply voltage applied to the SLIC.

Balanced current multiplier circuit for a subscriber loop interface

A circuit for use with a subscriber loop interface circuit (SLIC) to detect the hook/switch status of the telephone handset driven by the SLIC. Responsive to metallic current flowing through the handset when the telephone is taken off hook, a voltage is derived which exceeds a threshold level as well as a current is produced which is proportional to the value of the metallic current. Whenever the produced current level is less than a predetermined value in conjunction with the threshold level being exceeded, a comparator threshold circuit is rendered operative to produce a signal indicative of the hook status being in a closed switch state. With the hook being in an open switch state, the voltage is caused to be less than the threshold level wherein the comparator threshold circuit is maintained in an non-operative state.

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Mesa, AZ, United States of America

W Eric Main