International Business Machines Corporation

W David Pricer

Thomas M Shaw

Deborah A Neumayer

Robert B Laibowitz

John D Baniecki

Jack Allan Mandelman

William R Tonti

Ramachandra Divakaruni

Jed Hickory Rankin

Timothy Harrison Daubenspeck

Anthony Richard Bonaccio

William Thomas Motsiff

Russell J Houghton

Rosemary A Previti-Kelly

William A Klaasen

Michel S Michail

Kurt R Kimmel

A voltage supply bypass capacitor for use with a semiconductor integrated circuit chip or module comprising a ferroelectric dielectric having electromechanical properties designed to provide maximum losses at selected frequencies.

Tuneable ferroelectric decoupling capacitor

A method for configuring a bypass capacitor for use in conjunction with an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes selecting mechanical dimensions for the bypass capacitor, the mechanical dimensions causing the bypass capacitor to exhibit electrical losses at a clock frequency of the integrated circuit device. The bypass capacitor preferably includes a ferroelectric dielectric material. In addition, the selection of mechanical dimensions for the bypass capacitor determines a mechanical resonance frequency for the bypass capacitor, with the mechanical resonance frequency corresponding to the clock frequency.

A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.

Corrosion insensitive fusible link using capacitance sensing for semiconductor devices

There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

Method for novel SOI DRAM BICMOS NPN

An operational amplifier with two differential input stages is used to separately achieve low offset voltage and broad bandwidth characteristics. One input stage addresses dc and low frequency signals while the other addresses broadband frequencies. All transistors forming the dc stage are biased in the sub-threshold region. Following the two differential input stages, the signal paths are recombined in a capacitive cross-over network that provides outputs for subsequent amplification. The cross over frequency is adjustable from 15 kHz to 50 kHz using small practical values for the cross-over capacitor. The gain balance between the two input stages is adjustable by resistors and/or predetermined width/length ratios of the operational amplifier transistors.

Broadband dc amplifier technique with very low offset voltage

This is an integrated timing circuit which can be formed on a microprocessor chip. The circuit uses an oscillator having a delay line and a variable delay element. The delay line and the delay element vary together to hold the velocity of signal propagation in the circuit substantially constant. The output, of the oscillator is coupled to one input of a comparator circuit. A series of inverter circuits, each of which has a respective variable delay are connected to the input of the oscillator and to a second input of the comparator circuit such that the comparator circuit senses the difference between the output signal of the inverter series and the output signal of the oscillator circuit to provide an error signal proportional to the sensed difference. A feedback loop is provided, to the variable delay means in said oscillator and to the inverter circuits to correct for the sensed difference, to establish a uniform and stable time standard at the output of the oscillator.

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Charlotte, VT, United States of America

W David Pricer