Nvidia Corporation

Vyas Venkataraman

Mark Douglas Hummel

Samuel Hammond Duncan

Mark Hairgrove

Hemayet Hossain

Mark Alan Overby

Olivier Giroux

Naveen Cherukuri

Glenn A Dearth

Sanjeev Jain

Denis J Foley

John R Feehrer

Larry Robert Dennison

Lucien Dunning

Brian Kelleher

Ram Gummadi

Michael Asbury Woodmansee

Gobikrishna Dhanuskodi

Dwayne Frank Swoboda

Sudeshna Guha

Alexander Toichi Ishii

Geoffrey Gerfin

Nir Haim Arad

Philip John Rogers

Steven E Molnar

Vinod Grover

Lacky V Shah

Wishwesh Anil Gandhi

Vivek Kini

Jeffrey M Smith

Kyrylo Perelygin

Jonathon Stuart Ramsay Evans

Manjunath Kudlur

Piyush Patel

Vikram Sethi

Terje Bergstrom

Mayank Kaushik

Alban Douillet

Riley Andrews

Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.

High bandwidth extended memory in a parallel processing system

Apparatuses, systems, and techniques to generate a trusted execution environment including multiple accelerators. In at least one embodiment, a parallel processing unit (PPU), such as a graphics processing unit (GPU), operates in a secure execution mode including a protect memory region. Furthermore, in an embodiment, a cryptographic key is utilized to protect data during transmission between the accelerators.

Implementing trusted executing environments across multiple processor devices

Secure execution for multiple processor devices using trusted executing environments

Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Techniques for an efficient fabric attached memory

Multiprocessor clusters in a virtualized environment conventionally fail to provide memory access security, which is frequently a requirement for efficient utilization in multi-client settings. Without adequate access security, a malicious process may access what might be confidential data that belongs to a different client sharing the multiprocessor cluster. Furthermore, an inadvertent programming error in the code for one client process may accidentally corrupt data that belongs to the different client. Neither scenario is acceptable. Embodiments of the present disclosure provide access security by enabling each processing node within a multiprocessor cluster to virtualize and manage local memory access and only process access requests possessing proper access credentials. In this way, different applications executing on a multiprocessor cluster may be isolated from each other while advantageously sharing the hardware resources of the multiprocessor cluster.

Securing memory accesses in a virtualized environment

Distributed address translation in a multi-node interconnect fabric

A method for handling parallel processing clients associated with a server in a GPU, the method comprising: receiving a failure indication for at least client running a thread in the GPU; determining threads in the GPU associated with the failing client; exiting threads in the GPU associated with the failing client; and continuing to execute remaining threads in the GPU for other clients running threads in the GPU.

Selectively killing trapped multi-process service clients sharing the same hardware context

A method for analyzing race conditions between multiple threads of an application is disclosed. The method comprises accessing hazard records for an application under test. It further comprises creating a graph comprising a plurality of vertices and a plurality of edges using the hazard records, wherein each vertex of the graph comprises information about a code location of a hazard and wherein each edge of the graph comprises hazard information between one or more vertices. Additionally, it comprises assigning each edge with a weight, wherein the weight depends on a number and relative priority of hazards associated with a respective edge. Finally, it comprises traversing the graph to report an analysis record for each hazard represented in the graph.

Grouping and analysis of data access hazard reports

A system and method for debugging an executing program. The method includes executing a general-purpose computing on graphics processing units (GPGPU) program. The GPGPU program comprises a first portion operable to execute on a central processing unit (CPU) and a second portion operable to execute on a graphics processing unit (GPU). The method further includes attaching a debugging program to the first portion of the GPGPU program and modifying the first portion of the GPGPU program. The attaching of the debugging program to the first portion of the GPGPU program pauses execution of the first portion of the GPGPU program. The method further includes resuming execution of the first portion of the GPGPU program and accessing a first state information corresponding to the first portion of the GPGPU program. Execution of the first portion of the GPGPU program may then be paused. The first state information may then be used to access a second state information corresponding to the second portion of the GPGPU program.

System and method for debugging an executing general-purpose computing on graphics processing units (GPGPU) application

A system and method for detecting, filtering, prioritizing and reporting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises initialization information for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a potential conflict by identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. First information associated with a first access and second information associated with the second access to the location is determined. Filter criteria is applied to the first and second information to determine whether the instruction causes a reportable hazard. The instruction is reported when it causes the reportable hazard.

Method and system for heterogeneous filtering framework for shared memory data access hazard reports

Growing community of inventors

Santa Clara, CA, United States of America

Vyas Venkataraman