Cadence Design Systems, Inc.

Vuk Borich

Donald John O'Riordan

Keith Dennison

Hongzhou Liu

Jianzhou Zhao

Yue Li

Daniel De Fonseca Munford Argollo

A method including separating multiple signal waveforms into multiple blocks forming a sequence is provided. Each of the blocks includes at least a portion of each of the multiple signal waveforms. The method includes identifying a shared time portion and a shared signal portion for the signal waveforms within a first block from the multiple blocks and selecting a format for the first block based on a block size of the first block and a block read time of the first block. The method also includes compressing data in the first block based on the shared time portion, the shared signal portion, a preceding block and a subsequent block in the sequence, and storing the first block in a memory based on the format selected for the first block.

Adaptive lossless compression in analog mixed signal environments

Aspects of the present invention provide a system and method to estimate the amount of memory a harmonic balance analysis will require by measuring the memory allocated for a circuit database for a circuit undergoing harmonic balance analysis, determining the problem size of the harmonic balance analysis based on the information in the database, calculating the amount of memory for matrices, solution and auxiliary vectors needed for the harmonic balance analysis, and estimating the additional memory needed to complete a Newton iteration of the harmonic balance analysis using previously compiled statistical distributions. The total needed memory will be the sum of the measured, calculated, and estimated needed memory. A lower and an upper bound estimation of the total memory usage is provided. This information can be used by the circuit or system designer and/or an analysis or simulation tool for planning the computing resources necessary to execute the harmonic balance analysis.

Harmonic balance analysis memory usage estimation

A system, method, and computer program product for viewing analog simulation check violations in an EDA framework. Embodiments combine input data tables into a single data table for each check type using SQL inner join operations, create a SQL view of the single data table to list individual check violations, and output the view for user inspection of the corresponding check violations. Embodiments normalize the input data tables to include details of circuit nodes, elements, and paths implicated in the check violations. Additional views combine views of different check types into unified summary tables. Embodiments create a second view to aggregate individual check violations that involve the same circuit objects over time, and output the second view. Output views are self-describing, to enable a single graphical user interface to operate across multiple simulator versions. Metadata tables describe data types presented in various view columns, and user interactions allowed therewith.

Systems and methods for viewing analog simulation check violations in an electronic design automation framework

A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced circuit objects and parameterize the assertion for numerical values and connectivity. A designer may publish the assertion and annotate it with descriptive metadata, possibly with other assertions of related functionality, to a library accessible by users of analog design and verification tools. Another designer may re-use the assertion by searching for and selecting a relevant published assertion, instantiating and binding the selected assertion to specific elements of a second circuit design, and verify the assertion for the second circuit design.

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San Jose, CA, United States of America

Vuk Borich