Northern Telecom Limited

McMaster University

Vu Q Ho

Iain D Calder

Ismail T Emesh

Gurvinder Jolly

Lynnette D Madsen

Heinz Josef Nentwich

Hussein M Naguib

Abdalla A Naem

Jacques S Mercier

Hussein M Naquib

A capacitor structure for a memory element of an integrated circuit is provided. The capacitor is formed within a via hole defined through a first dielectric layer, and comprises a bottom electrode defined by an underlying conductive layer, and a capacitor dielectric filling the via with a dielectric barrier layer lining the via and separating the capacitor dielectric from the first dielectric layer. The capacitor dielectric is characterized by a material with high dielectric strength, preferably a ferroelectric material. An overlying conductive layer defines a top electrode contacting the capacitor dielectric. The barrier layer may comprise dielectric sidewall spacer formed within the via, or alternatively may comprise a region of mixed composition formed by interdiffusion of the first dielectric layer and the capacitor dielectric. The resulting capacitor structure is simple and compact, and may be fabricated with known CMOS, Bipolar or Bipolar-CMOS processes for submicron VLSI and ULSI integrated circuit.

Structure and method of making a capacitor for an intergrated circuit

A method is provided for forming a capacitor structure for a memory element of an integrated circuit. The method comprises providing a first conductive electrode, forming a layer of a first dielectric material thereon, opening a via hole through the dielectric layer, providing within the via opening a capacitor dielectric having a higher dielectric strength than the first dielectric, the capacitor dielectric contacting the first electrode, planarizing the resulting structure and then forming a second conductive electrode thereon. Preferably, when the second dielectric comprises a ferroelectric dielectric material, sidewalls of the via opening are lined with a dielectric barrier layer to provide diffusion barrier between the ferroelectric and first dielectric layer. Advantageously, planarization is accomplished by chemical mechanical polishing to provide fully planar topography. The method provides a capacitor of a simple, compact structure which may be integrated with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuits.

Method of making a capacitor for an integrated circuit

In methods for making interconnect structures for semiconductor devices a layer of seed material is formed on a first substantially planar dielectric layer which covers the semiconductor devices at predetermined locations where interconnect conductor is desired, a second substantially planar dielectric insulating layer is formed over the first substantially planar dielectric insulating layer and the seed material, the second layer having openings extending therethrough at the predetermined locations to expose at least a portion of the seed material, and conductive material is selectively deposited on the exposed seed material to fill the openings. The seed material may be a material in the group consisting of aluminum alloys, refractory metals and metal silicides, or may be SiO.sub.2 selectively implanted with silicon ions. The insulating material may be SiO.sub.2. The conductive material used to fill the openings may be tungsten deposited by selective CVD or nickel deposited by selective electroless nickel plating. The steps of the methods may be repeated to form a multilevel interconnect structure. The methods are particularly suited to making interconnect structures for submicron devices.

Method for making interconnect structures for VLSI devices

In a method of filling a contact hole of a semiconductor device, a layer of conducting material, such as a metal silicide, is formed on side walls of the contact hole, and metal is selectively deposited on the bottom of the contact hole and on the layer of metal silicide on the side walls of the contact hole to substantially fill the contact hole. The method provides a contact structure comprising a contact region of the semiconductor device defining the bottom of the contact hole, a layer of conducting material, such as a metal silicide, on the side walls of the contact hole, and a metal plug substantially filling the contact hole. The metal plug adheres to the layer of metal silicide on the side walls of the contact hole and to the contact region defining the bottom of the contact hole.

Method of filling contact holes for semiconductor devices and contact

In a metal oxide semiconductor field effect transistor fabrication process, refractory metal is deposited over designated source and drain areas within a silicon substrate. Refractory metal and silicon at the interface is then mixed by ion implantation of a heavy neutral ion species such as germanium. To minimize source/drain junction depth, the source and drain locations can be subjected to bombardment by a lighter ion such as silicon which amorphizes silicon to a predetermined depth under the designated source and drain regions and so substantially confines dopant diffusion to the silicon amorphized region. To render the source and drain of desired conductivity type, an ion implantation of a non-neutral ion is then performed.

Process of fabricating MOS devices having shallow source and drain

Particularly for use in MOS (metal-oxide-semiconductor) VLSI (very large scale integrated) circuits, an aluminum conductor coated with a layer of refractory metal or refractory metal silicide has the advantages of being resistant both to electromigration and to hillock growth. By this invention, to reduce the resistivity of this composite conductor and to eliminate hillock formation, the conductor is subjected to an ion implantation step to cause interface mixing between the aluminum and the adjacent refractory metal or refractory metal silicide.

Forming low resistivity hillock free conductors in VLSI devices

Particularly for use in multilevel metallization structures in which the underlying topography consists of fine and sharply contoured conductor lines produced by dry etching, conformal or near planar dielectric coatings are produced by depositing a dielectric layer to a thickness over the conductor of at least three times the conductor thickness. The dielectric is then anisotropically etched back to a thickness comparable with that of the underlying conductor. By this method a smooth dielectric top surface can be obtained without the requirement for multiple processing steps characterizing alternative planarizing techniques.

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Kanata, Canada

Vu Q Ho