International Business Machines Corporation

Endicott Interconnect Technologies, Inc.

I3 Electronics, Inc.

Other

International Business Corporation

Endicott International Technologies, Inc.

Maines Paper and Food Service, Inc.

Voya Rista Markovich

John M Lauffer

William E Wilson

Frank Daniel Egitto

Kostas I Papathomas

Anilkumar Chinuprasad Bhatt

Rabindra N Das

Roy H Magnuson

How Tzu Lin

David L Thomas

David John Russell

Douglas Oliver Powell

Benson Chan

Thomas R Miller

Konstantinos I Papathomas

Mark David Poliks

Robert Maynard Japp

Ross William Keesler

Carlos Juan Sambucetti

Anthony P Ingraham

Donald Seton Farquhar

Stephen L Tisdale

Elizabeth F Foster

Miguel Angel Jimarez

Gerald Walter Jones

Michael Wozniak

Luis Jesus Matienzo

Christina Marie Boyko

Ashwinkumar C Bhatt

Kenneth Michael Fallon

Stephen Joseph Fuerniss

Alfred Viehbeck

William John Rudik

Donald Herman Glatzel

Perminder S Bindra

William Louis Brodsky

Mark Vincent Pierson

Martin J Goldberg

Sanjeev Balwant Sathe

Irving Memis

Raymond Thomas Galasco

Harry R Bickford

John A Welsh

Linda C Matthew

Michael A Gaynes

Terrence Robert O'Toole

Bruce John Chamberlin

Charles Hampton Perry

John Steven Kresge

Bernd Karl Appelt

Lisa Jeanine Jimarez

Richard A Schumacher

Donald G McBride

Jeffrey Alan Knight

Issa S Mahmoud

Sampath Purushothaman

George Frederick Walker

Sung Kwon Kang

David W Wang

James Warren Wilson

Donald P Seraphim

Brenda Lee Peterson

Francis Joseph Downes, Jr

George Henry Thiel

John Ulrich Knickerbocker

Paul Alfred Lauro

Roy Rongqing Yu

Jeffrey Donald Gelorme

Richard Hsiao

Jane M Shaw

Jerome J Cuomo

Eric D Perfecto

Claudius Feger

David Noel Light

Lewis Sigmund Goldmann

Chandrika Prasad

Gary A Johansson

John Gerard Gaudiello

Edwin Lorimer Thomas

David Erle Houser

Ajit Kumar Trivedi

John J Ritsko

Giulio DiGiacomo

Ajay Prabhakar Giri

Brian Eugene Curcio

Thomas P Gall

Timothy Leroy Wells

Thurston Bryce Youngs, Jr

Brian Samuel Beaman

Michael B Vincent

Jeffrey Curtis Hedrick

James A Busby

Natalie Barbara Feilchenfeld

James Robert Wilcox

David V Caletka

John Joseph Konrad

Suryadevara Vijayakumar Babu

Bahgat Ghaleb Sammakia

Sandeep B Sane

Amit Kumar Sarkhel

A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.

Method of making a circuitized substrate

A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.

Electrically conductive adhesive (ECA) for multilayer device interconnects

A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

Coreless layer buildup structure with LGA and joining layer

A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

Conducting paste for device level interconnects

A structure for minimizing resistance between a semi-insulating x-ray detector crystal and an electrically conducting substrate. Electrical contact pads are disposed on the detector crystal and on the substrate with an electrical interconnect between the contact pads formed from a conductive adhesive and washed solder in electrical and mechanical communication with the pads.

Solder and electrically conductive adhesive based interconnection for CZT crystal attach

An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.

Electronic package with thermal interposer and method of making same

A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.

Coreless layer buildup structure

Coreless layer buildup structure with LGA

Printed conductive lines and a method of preparing them using polymer nanocomposites with low resistivity and high current carrying capacity. Plasma treatment selectively removes polymers/organics from nanocomposites. Subsequent selective metal is deposited on top of the exposed metal surface of the printed conductive lines in order to improve current carrying capacity of the conductive printed lines. The printed conductive lines use a conductive ink or printing process and are then cured thermally and/or by a lamination process. Next, the printed conductive lines are treated with the plasma for 5-15 minutes in order to remove organics. E-less copper (Cu) is selectively deposited only at the conducting particle surface of the printed conductive lines. If desired, e-less gold, silver, tin, or tin-lead can be deposited on top of the e-less Cu.

Method of forming an electrically conductive printed line

Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

Method of forming multilayer capacitors in a printed circuit substrate

A method of making a circuitized substrate including a composite layer having a first dielectric sub-layer including a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein.

Method of making halogen-free circuitized substrate with reduced thermal expansion

A low loss capacitance and low loss insulating dielectric material consisting of a thermosetting resin, thermoplastic resin, a cross-linker, and containing a quantity of ferroelectric ceramic nano-particles of barium titanate within. The combined low loss insulating dielectric layer and a low loss capacitive layer resulting from the material allows one continuous layer that can form internal capacitors and permit the modifying the dielectric thickness between signal layers for impedance matching within a layer of substrate. More significantly, the applied layer of low loss capacitive materials can simultaneously act as a capacitor as well as a dielectric for separation of signal layers.

Circuitized substrate with low loss capacitive material and method of making same

An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors. Circuitized substrate assemblies using the electronic packages of the invention are also provided.

Electronic package including high density interposer and circuitized substrate assembly utilizing same

A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.

Circuitized substrate with dielectric interposer assembly and method

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Anti-tamper microchip package based on thermal nanofluids or fluids

Growing community of inventors

Endwell, NY, United States of America

Voya Rista Markovich