Intersil Corporation

Intersil Americas Inc.

Volodymyr A Muratov

Thomas Andrew Jochum

Robert G Hodgins

Michael Coletta

Wlodzimerz S Wiktor

A DC/DC converterhas a DACthat receives a code associated with desired processor operating voltage and sets the reference voltage on its output. The reference voltage (V) is boosted by the buffer amplifierto center the droop along the median load. A sensed current signal Iis proportional to the load current Iand can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain G. A droop control feedback circuit includes an error amplifier. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency Fand transformed to the current Ithat creates the voltage drop across the resistor R. The other input is coupled to the buffer amplifier output. As a result, the output voltage of the converteris inversely proportionally to the load current and is invariant to the processor clock frequency changes associated with the processor mode switchover. Other embodiments modify the gain of the error amplifier, or offset the gain and hold the amount of droop constant.

Methods to control the droop when powering dual mode processors and associated circuits

A DC/DC converter has a DAC that receives a code associated with desired processor operating voltage and sets the reference voltage on its output . The reference voltage (V ) is boosted by the buffer amplifier to center the droop along the median load. A sensed current signal I is proportional to the load current I and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain G . A droop control feedback circuit includes an error amplifier . It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency F and transformed to the current I that creates the voltage drop across the resistor R . The other input is coupled to the buffer amplifier output. As a result, the output voltage of the converter is inversely proportionally to the load current and is invariant to the processor clock frequency changes associated with the processor mode switchover. Other embodiments modify the gain of the error amplifier, or offset the gain and hold the amount of droop constant.

A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.

Growing community of inventors

Durham, NC, United States of America

Volodymyr A Muratov