International Business Machines Corporation

Volker Urban

Reinhard Theodor Buendgen

Richard Victor Kisley

Eric David Rossman

Harald Freudenberger

Christian Jacobi

Jonathan D Bradbury

Khary J Alexander

Bernd Nerz

Markus Helms

Michael D Hocker

Joerg H Walter

Norbert Schumacher

Damian Leo Osisek

Tamas Visegrady

Louis P Gomes

Juergen Koehl

Klaus Werner

Richard John Moore

Juergen Saalmueller

Viktor Mihajlovski

Lothar Felten

Walter Pietschmann

Torsten Hendel

Marcel Naggatz

Benedikt Klotz

Markus Selve

Steffen Eiden

According to one embodiment, a method, computer system, and computer program product for establishing identity-based hierarchical sessions on a hardware security module (HSM) for binding secure keys to a guest system, is disclosed. The present invention may include establishing a communication channel between the guest system and the HSM, wherein the communication channel is identity-based, end-to-end and encrypted, thereby establishing a session, transferring login information of the guest system through the communication channel to the HSM, maintaining a predefined security level throughout a hierarchy of the sessions, wherein no child session has a higher security level than its parent session, and performing a challenge-response protocol based on a session ownership verification with the guest, such that an HSM generated and secured key is bound to a related session.

Identity based hierarchical sessions

A method for a policy-based association of a hardware security module to a secure guest is disclosed. The method comprises maintaining a binding between a secure guest and an HSM. Thereby, the binding enables the trusted guest to send only non-sensitive request to the HSM. The method comprises further maintaining, for a secure guest, a pair of a secret and a secret name, submitting a query to the bound HSM for obtaining HSM configuration data, and upon determining that the obtained HSM configuration data match a rule available to the secure guest, wherein the rule associates the HSM to a secret name, requesting to associate the secret from the pair of secret and the secret name to the bound HSM, thereby triggering that the trusted firmware allows the secure guest to submit a sensitive crypto-request to the bound and associated HSM.

Selecting an HSM for association to a secure guest

A message limit value to be used in enqueuing one or more messages on a queue of a device of the computing environment is obtained. The message limit value indicates whether an extended maximum message length is supported by the device. The extended maximum message length is different from a default maximum message length supported by the device. Based on determining that the extended maximum message length is supported and that the obtained message limit value has a defined relationship with a select value, at least one message of an extended length is enqueued on the queue of the device.

Adjunct processor extended message limit facility

At least one secure object of a security module is bound to a secure guest. A trusted component determines whether metadata of the secure guest includes a confidential binding attribute for the security module. Based on determining that the metadata includes the confidential binding attribute, the trusted component configures the security module for the secure guest in a select mode. The select mode prevents certain operations from being intercepted by a hypervisor associated with the secure guest. The trusted component intercepts a security module communication and performs a cryptographic operation on one or more secure objects of the security module communication using the confidential binding attribute to provide a cryptographic result. An outcome of the security module communication, which includes the cryptographic result, is provided to a receiver.

Binding secure objects of a security module to a secure guest

A security module, such as a cryptographic adapter, is reserved for a secure guest of a computing environment. The reserving includes binding one or more queues of the security module to the secure guest. The one or more queues are then managed based on one or more actions relating to the reservation.

Reserving one or more security modules for a secure guest

A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.

Resource mapping in multi-threaded central processor units

A method for simulating an operation of a digital circuit () is described. The method utilizes cycle simulation, wherein in a cycle based simulation model () of the digital circuit () components () of the digital circuit () are clocked synchronously every cycle () of a functional clock (Clk). According to the invention, real digital circuit (), i.e. chip or combinatorial logic (), timing information is included in the cycle simulation by inserting delay latches () into the cycle based simulation model () of the digital circuit (), wherein a non-functional clock (Sim clock) is used to clock the delay latches (), so that each delay latch () delays the propagation of a signal (I, J, K) by a cycle () of the non-functional clock (Sim clock).

Simulating an operation of a digital circuit

The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.

Method for validating logical function and timing behavior of a digital circuit decision

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Boeblingen, Germany

Volker Urban