Siemens Aktiengesellschaft

Infineon Technologies Ag

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Volker Thomas

Stephan Weber

Bernd Adler

Josef Fenk

Stefan Herzinger

Herbert Stockinger

Josef Schmal

Umut Basaran

Elmar Wagner

Alexander Belitzer

Andre Hanke

Wolfgang Thomann

Boris Kapfelsperger

The disclosed invention relates to a transceiver system comprising a notch filter element configured to suppress transmitter blockers (i.e., transmitter interferer signals) within a reception path. In some embodiments, the transceiver front-end comprises a differential reception path, having a first differential branch and a second differential branch, configured to provide an RF differential input signal having a transmitter blocker to a transimpedance amplifier, comprising a first-order active filter and a notch filter element. The notch filter element comprises a stop band corresponding to a frequency of a transmitted signal, such that the notch filter element suppresses the transmitted blocker without degrading the signal quality of the received differential input signal.

Second-order filter with notch for use in receivers to effectively suppress the transmitter blockers

A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal. The mismatch compensator is configured to receive the signal generator output signal and compensate a frequency mismatch between a desired signal generator output frequency and the signal generator output frequency generated by the oscillator by providing the fine tuning signal for changing the state of the fine tuning circuit of the oscillator and by providing the coarse tuning signal for changing a state of the coarse tuning circuit of the oscillator. The mismatch compensator provides the coarse tuning signal during a guard period defined in the given communication protocol, during which no RF-signals are transmitted by the transmitter or no RF-signals are to be received by the receiver, such that the state of the coarse tuning circuit is changed within the guard period.

Signal generator for a transmitter or a receiver, a transmitter and a receiver

Various embodiments of a wireless multimode receiver having an off-chip duplex filter associated with a multimode band, and a blocker cancellation circuit disposed on a semiconductor chip are described in the present disclosure.

Multimode receiver with active blocker suppression

To keep the power consumption in the modulator-demodulator of a mobile radio as low as possible, the modulator-demodulator has a voltage-controlled oscillator. Downstream of which a divider chain having a plurality of series-connected dividers each with an even-numbered division factor is connected. Each of the dividers produces a carrier signal and a carrier signal that is orthogonal with respect thereto. A quadrature modulator for the received signal is connected to a divider of the divider chain that produces the carrier signal at the required carrier frequency. In addition, a first vector modulator is provided whose mixers are connected to the dividers of the divider chain that produce the carrier signals at the required carrier frequencies. Connected downstream of the first vector modulator is a further divider with an even-numbered division factor, and connected downstream of this is a second vector modulator for producing a transmitted signal.

Modulator-demodulator

An interface circuit for transmitting binary signals includes a signal transmitting device, a signal receiving device and a transmission device connected therebetween. The signal transmitting device has a device for limiting steepness of ascending and descending edges of the binary signals to certain inclination values which are identical to one another.

Interface circuit

A circuit for determining and evaluating a data signal with a disturbing direct voltage portion has a signal processor with which the direct voltage portion is determined and then subtracted from the signal. A non-linear control is provided that changes a time constant of the circuit in dependence on the signal curve.

Circuit for determining and evaluating a data signal on which a direct

A circuit configuration for offset compensation includes a filter device for ascertaining a direct component in an input signal delivered to it and a linking device for subtractive linking of the input signal and an output signal of the filter device. A tracking and holding device which is connected between the filter device and the linking device is controllable by a control signal. The control signal is furnished by a window comparator device having an input to which the input signal is applied. When the input signal is within a predetermined window, the tracking and holding device is located in a tracking mode, while otherwise it is in a holding mode.

Circuit configuration for offset compensation

A low-pass filter circuit including a first sub-filter designed in integrated circuit technology. The first sub-filter includes high-impedance resistor elements and smaller capacitances. A second sub-filter preceding the first sub-filter is constructed with low-impedance resistor elements and higher capacitances.

Filter circuit arrangement

A bipolar cascadable circuit configuration includes a limiter stage generating an output signal. A detection stage receives the output signal from the limiter stage and supplies an output signal. A power supply receives a supply voltage and feeds an output current to the detection stage. The power supply and the output signal of the detection stage are dependent on the supply voltage. A configuration for compensating for fluctuations in the power supply forms a difference between a first, early-dependent current and a second, less early-dependent current, multiplies it by a factor and adds it to the output current of the power supply.

Bipolar cascadable circuit configuration for signal limitation and field

An integratable current source circuit for generating an output current proportional to an input current includes a first transistor of one conduction type, and second, third and fourth transistors of the other conduction type. Each of the transistors has a base, a collector and an emitter. The first transistor has a current amplification being greater than current amplifications of the second, third and fourth transistors. An input terminal feeds an input current, and an output terminal taps an output current. A current source on one hand is connected to a reference potential and on the other hand is connected to the emitter of the first transistor and to the base of the second transistor. The collector of the second transistor is connected to the reference potential and the emitter of the second transistor is coupled to the base of the third transistor and to the base of the fourth transistor. The base of the first transistor is connected to the collector of the third transistor and to the input terminal. The collector of the fourth transistor is connected to the output terminal. The collector of the first transistor and the emitters of the third and fourth transistors are connected to a supply potential.

Integratable current source circuit for generating an output current

An integrated circuit includes first and second oscillators. A controllable switch has a signal input connected to a signal output of the second oscillator. A modulator has two signal inputs each being coupled to a signal output of a respective one of the first oscillator and the controllable switch. At least one controllable reversing switch has two signal inputs each being connected to a signal output of a respective one of the modulator and the controllable switch. A controllable frequency divider has a signal input connected to a signal output of the second oscillator. Two signal input terminals are each connected to a modulation input of a respective one of the oscillators, and two input terminals are each connected to the frequency control input of a respective one of the oscillators. Signal output terminals are each connected to the signal output of a respective one of the first oscillator, the at least one controllable reversing switch, the frequency divider, and the second oscillator. Control terminals are respectively connected to the control input of the frequency divider, to the control input of the controllable switch and the switch input of the first oscillator, and to the control input of the at least one controllable reversing switch.

Growing community of inventors

Gilching, Germany

Volker Thomas