Infineon Technologies Ag

Volker Sch&ouml;ber

Steffen Paul

Rod G Fleck

Yannick Martelloni

Sabeen Randhawa

Mario Di Ronza

Klaus Oberl&auml;nder

Olivier Caty

Laurent Gaziello

Olivier Picot

Paolo Ienne

The invention relates to an integrated bus signal hold cell that is coupled with a bus line via a common input/output, and that has at least two inverters for holding the last state of the bus line. The outputs of the inverters are coupled with each other's inputs, respectively. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output. An additional input is provided via which the bus signal hold cell can be charged with a defined test signal. The invention also relates to an integrated bus system and a method for driving a bus signal hold cell and a bus system.

Bus signal hold cell, bus system, and method

A data memory including a main data memory having a plurality of data memory units, a redundancy data memory that includes a plurality of redundancy data memory units for the replacement of defective data memory units of the main data memory, and a redundancy control logic for controlling the access to the redundancy data memory, the main data memory and the redundancy data memory being connected to a data bus in parallel with one another via data lines, and the main data memory and the redundancy control logic being connected, in parallel with one another, via address lines, to an address bus for the addressing of data memory units in the data memory.

Data memory with short memory access time

A semiconductor memory device includes a plurality of integrated circuit modules each having a plurality of module elements and at least one adjustable module element. At least one fuse box is electrically connected to the plurality of integrated circuit modules. The fuse box has a plurality of programmable fuse elements, that, when programmed, adjust the adjustable module element.

Circuit device having a fuse

The circuit cell for test methods having a built-in self-test function for modular circuits. The cell has a memory unit for storing data, a combinatorial logic circuit for data processing, and a memory control unit for controlling the memory unit. The memory control unit can be configured such that it sets the memory unit as a test pattern generator in a transmission mode and sets it as a test pattern compression device in a reception mode. The memory control unit produces a synchronizing signal for synchronizing the memory unit on the basis of communication signals which are interchanged by the memory control unit and memory control units in further circuit cells. With these methods, a transmission circuit cell is synchronized locally, so that a global clock signal is not required.

Circuit cell having a built-in self-test function, and test method therefor

The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units. The serviceability of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.

Growing community of inventors

München, Germany

Volker Schöber

Growing community of inventors

München, Germany

Volker Sch&ouml;ber

Volker Schöber