Altera Corporation

Volker Mauer

Martin Langhammer

Suleyman Sirri Demirsoy

Zhengjun Pan

Shahin Gheitanchi

David Lewis

Henry Y Lui

Keone Streicher

Hyun Mo Yi

Yi-Wen Lin

Wai-Bor Leung

Nima Safari

Steven Perry

Paul Metzgen

Kulwinder Singh Dhanoa

Lei Xu

Colman Cheung

James Tyson

Benjamin Thomas Cope

Richard Maiden

Kellie Marks

Mark Jervis

Alejandro Diaz-Manero

Benjamin Thomas Cop

A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.

Fast fourier transform (FFT) based digital signal processing (DSP) engine

Integrated circuits with wireless communications circuitry are provided. The wireless communications circuitry may include an input FIFO, an output FIFO, a processing module interposed between the input and output FIFOs, and dynamic power control circuitry that controls the performance of the processing module. The input and output FIFOs may provide fill level information to the processing module. The dynamic power control circuitry may analyze the current fill level information received from the input and output FIFOs and may increase the operating frequency and/or boost the power supply voltage of the processing module in response to detecting that the input FIFO is filling up faster than the output FIFO or may decrease the operating frequency and/or reduce the power supply voltage of the processing module in response to detecting that the output FIFO is filling up faster than the input FIFO.

Methods and apparatus for performing buffer fill level controlled dynamic power scaling

An arithmetic processing block in which two inputs are provided for a multiplier, the block also including a pre-adder for combining the inputs to provide an additional option for a multiplier input.

Flexible input structure for arithmetic processing block

A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.

Pipelined systolic finite impulse response filter

Digital signal processing ('DSP') block circuitry on an integrated circuit ('IC') is adapted for use, e.g., in multiple instances of the DSP block circuitry on the IC, for implementing finite-impulse-response (&#x201c;FIR&#x201d;) filters that are dynamically adjustable. Advantages of such DSP block circuitries may include an increase in performance and a reduction in logic and memory usage for multi-standard FIR filters.

Dynamically programmable digital signal processing blocks for finite-impulse-response filters

Circuitry that efficiently implements loop functions in an integrated circuit is provided. The circuitry combines a feed-forward circuit with a feedback loop that includes a unit delay element in a feedback path. The feedback path may couple the output of a processing element to the input of the processing element. The processing element may implement a function that satisfies commutative, associative, and distributive properties. Combining the feedback loop with the feed-forward circuit may allow for register retiming in the feedback loop and for register pipelining with optional register retiming in the feed-forward circuit. The circuitry may thus trade off an increase in throughput and clock frequency for additional resources.

Methods and apparatus for implementing feedback loops

Integrated circuits with wireless communications circuitry having peak cancelation circuitry operable to perform crest factor reduction is provided. The peak cancelation circuitry may receive at least first and second carrier waveforms and may include at least a first canceling pulse generator (CPG), a second CPG, a first peak detector for performing peak detection on the first waveform, a second peak detector for performing peak detection on the second waveform, a third peak detector for performing peak detection on a combined waveform of the first and second waveforms, and a pulse allocator that receives clipping information from the three peak detectors and that controls the amount of peak cancelation that is being performed by the two CPGs. The allocator may determine whether the combined waveform contains any peaks. In response to determining that the combined waveform does not contain any peaks, the CPGs may be configured in bypass mode.

Multi-standard peak canceling circuitry

Integrated circuits are provided with wireless communications circuitry having digital predistortion (DPD) circuitry, peak canceling circuitry, a power amplifier, and signal conditioning circuitry for controlling the DPD and peak canceling circuitry. The peak canceling circuitry may receive transmit signals and may clip peaks in the transmit signals that exceed a magnitude threshold value. The DPD circuitry may compensate for non-linear characteristics of the power amplifier by outputting a predistorted version of the clipped transmit signals. The power amplifier may receive the predistorted signals and may perform amplification to generate amplified signals. The signal conditioning circuitry may identify power transfer characteristics of the power amplifier and DPD circuitry using the predistorted signals and the amplified signals. The signal conditioning circuitry may update the magnitude threshold value imposed by the peak canceling threshold based on the identified power transfer characteristics to mitigate out-of-band spectral regrowth in the predistorted signals.

Methods and apparatus for adjusting transmit signal clipping thresholds

Integrated circuits with wireless communications circuitry having digital predistortion (DPD) circuitry are provided. The digital predistortion circuitry may include a forward path filter, a time domain alignment (TDA) circuit, a frequency domain alignment (FDA) circuit, and an adaption circuit. The TDA circuit may receive power amplifier input signals and power amplifier output signals and may include a cross correlator, a peak detector, and a delay circuit for performing coarse time domain alignment (i.e., to align the power amplifier input and output signals). The FDA circuit may include a fast Fourier transform circuit, a matrix multiplier, and a matrix inverter for performing frequency domain alignment. The adaption circuit may analyze the aligned signals output from the FDA circuit to produce impulse response coefficients that are then used to control the forward path filter. The forward path filter may serve to predistort transmit signals prior to radio-frequency amplification.

Methods and apparatus for performing digital predistortion using time domain and frequency domain alignment

Efficient matrix operations circuitry is based on combining a matrix decomposition and a forward substitution operations to share the same processing overhead. A dual multiplier circuit selectively applies complex multiplication operations to a first and second input vectors for computing a conjugate dot product vector or a non-conjugate dot product vector. The conjugate dot product vector corresponds to the matrix decomposition operation for triangulating an input matrix to generate an element of a triangulated matrix. The non-conjugate dot product vector corresponds to a forward substitution operation for determining an element of a forward substitution vector from the triangulated matrix.

Matrix operations in an integrated circuit device

A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.

Resource sharing in decoder architectures

Circuitry for performing QR decomposition of an input matrix includes multiplication/addition circuitry for performing multiplication and addition/subtraction operations on a plurality of inputs, division/square-root circuitry for performing division and square-root operations on an output of the multiplication/addition circuitry, a first memory for storing the input matrix, a second memory for storing a selected vector of the input matrix, and a selector for inputting to the multiplication/addition circuitry any one or more of a vector of the input matrix, the selected vector, and an output of the division/square-root circuitry. On respective successive passes, a respective vector of the input matrix is read from a first memory into a second memory, and elements of a respective vector of an R matrix of the QR decomposition are computed and the respective vector of the input matrix in the first memory is replaced with the respective vector of the R matrix.

QR decomposition in an integrated circuit device

Digital signal processing ('DSP') circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response ('FIR'), digital filters.

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Princes Risborough, United Kingdom

Volker Mauer