Infineon Technologies Ag

Volker Kilian

Richard Roth

Martin Perner

Stefan Sommer

Lenart Hauptner

Martin Brox

Wolfgang Anton Spirkl

Robert Kaiser

Thorsten Bucksch

Martin Meier

The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.

Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods

A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same loads during manufacturing and test processes, and that at least one regular memory cell from a regular memory area and at least one redundant memory cell from a redundant memory area are connected with each other via a coupling circuit. The coupling circuit, in particular during the testing of the operability of the semiconductor memory device or of the memory cells, respectively, determines the state of the regular memory cell and/or the redundant memory cell. Thus, in tested and repaired semiconductor memory devices, so-called redundancy storage space for the repair of defective memory capacity can be provided for repair even in the last memory test step, including full test severity and fulfilling all and any reliability requirements for the repair of high-grade memory devices.

Memory device and method for testing memory devices with repairable redundancy

The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data into or from a semi-conductor component, whereby the semi-conductor component comprises one or more useful data memory cells, and/or one or more test data and/or semi-conductor component operating control data registers for storing test data and/or semi-conductor component operating control data, and whereby the process comprises the steps of applying a control signal to the semi-conductor component, whereby the semi-conductor component is switched from a first to a second operating mode; and applying an address signal to the semi-conductor component, whereby one or more of the test data and/or semi-conductor component operating control data registers of the semi-conductor component is addressed by the address signal in the second operating mode, and one or more of the useful data memory cells in the first operating mode.

Semi-conductor component, as well as a process for the in-or output of test data

A tuning circuit for setting a signal propagation time on a signal line in an integrated circuit, particularly a DRAM circuit, has a transistor and a capacitor. A control connection of the transistor is connected to a control unit for the purpose of switchably connecting the capacitor to the signal line through the transistor in order to set the signal propagation time on the signal line on the basis of application of a control signal, generated in the control unit, to the control connection on the transistor.

Circuit for setting a signal propagation time for a signal on a signal line and method for ascertaining timing parameters

To generate test signals by a test logic unit on a semiconductor wafer, the test signals being used to check specific functions and/or parameters of an integrated circuit on the semiconductor wafer, at least two test signals are provided substantially simultaneously by the test logic unit and are subsequently serialized to generate a multiplexed test signal sequence with a data rate required for testing.

Method for generating test signals for an integrated circuit and test logic unit

In the case of the present-day trend of miniaturizing housed electronic devices, there is the problem that the contact spacings between the terminal pins becomes smaller and smaller and are no longer visible optically. As a result, it also becomes more difficult to solder the contacts of correspondingly designed contact bases, which for example, are designed as test bases, to the individual conductor tracks of the printed circuit board. Possible faulty soldering points, short circuits or interruptions have hitherto been tracked down by laborious manual measurement using the TDR method. The invention proposes producing a test device in which in each case two terminal pins are connected to a short-circuiting bridge. The test device is inserted into the contact base and connects two signal paths of the printed circuit board on which the propagation time of a reflected wave can be measured.

Method and apparatus for finding a fault in a signal path on a printed circuit board

The invention relates to a method for measuring the junction temperature in an electronic component. A periodic test signal is led via a signal path inside the component in order to obtain an internal signal. There is a frequency and/or phase relationship between the periodic test signal and a periodic external signal. A phase shift is measured between the internal signal and the external signal. The junction temperature is determined over the component region determined by the signal path as a function of the phase shift.

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Munich, Germany

Volker Kilian