Advanced Micro Devices Corporation

Globalfoundries Inc.

Volker Grimm

Ralf Richter

Heike Salz

Kai Frohberg

Christian Krueger

Ronald Naumann

Thorsten E Kammler

Matthias Lehr

Matthias Schaller

Joerg Hohage

Thomas Feudel

Christoph Schwan

Gunter Grasshoff

Dmytro Chumakov

Martin Mazur

Heike Berthold

Sven Mueller

Lutz Eckart

Andrey Zakharov

Jochen Klais

Tino Meinhold

When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.

Enhancing transistor performance by reducing exposure to oxygen plasma in a dual stress liner approach

In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

Shrinkage of critical dimensions in a semiconductor device by selective growth of a mask material

By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.

Method for selectively removing a spacer in a dual stress liner approach

Resist masks exposed to high-dose implantation processes may be efficiently removed on the basis of a combination of a plasma-based etch process and a wet chemical etch recipe, wherein both etch steps may include a highly selective etch chemistry in order to minimize substrate material loss and thus dopant loss in sophisticated semiconductor devices. The first plasma-based etch step may provide under-etched areas of the resist mask, which may then be efficiently removed on the basis of the wet chemical etch process.

Technique for removing resist material after high dose implantation in a semiconductor device

By forming an etch control material with increased thickness on a first stressed dielectric layer in a dual stress liner approach, the surface topography may be smoothed prior to the deposition of the second stressed dielectric material, thereby allowing the deposition of an increased amount of stressed material while not contributing to yield loss caused by deposition-related defects.

Stressed interlayer dielectric with reduced probability for void generation in a semiconductor device by using an intermediate etch control layer of increased thickness

By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

In a method of forming a semiconductor structure, a substrate comprising at least one contact pad is provided. A passivation layer is formed over the substrate. A mask which does not cover a portion of the passivation layer located over the at least one contact pad is formed over the passivation layer. An etching process adapted to remove a material of the passivation layer is performed and the mask is removed. Then, a second etching process adapted to remove residues of the passivation layer from the contact pad can be performed. The removal of the mask may be performed at a temperature of the substrate in a range from about &#x2212;20&#xb0; C. to about 100&#xb0; C. The second etching process can comprise exposing the substrate to a gaseous etchant comprising hydrogen and fluorine, an amount of hydrogen in the etchant being about equal to an amount of fluorine, or greater. Thus, a formation of oxides and/or fluorides on the at least one contact pad can be avoided.

Method of forming contact pads

The present invention discloses a technique for controlling a local etch rate in forming multi-level contact openings, for example, in forming substrate contact openings and transistor contact openings of an SOI device. The aspect ratio dependent etch rate is correspondingly adapted by selecting in advance suitable aspect ratios for the contact openings so that the etch front may reach the respective final depth within a limited time interval.

Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process

In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.

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Langebrueck, Germany

Volker Grimm