3-5 Power Electronics Gmbh

Atmel Germany Gmbh

Atmel Corporation

Telefunken Semiconductors Gmbh & Co. Kg

Other

Azur Space Solar Power Gmbh

Robert Boschgmbh

Atmel Automotive Gmbh

Azur Space

Volker Dudek

Michael Graf

Franz Dietz

Stefan Schwantes

Manfred Klaussner

Gayle W Miller

Christoph Bromberger

Joern Herrfurth

Daniel Fuhrmann

Harry Dietrich

Riteshkumar Bhojani

Jens Kowalsky

Irwin Rathbun

Andreas Schueppen

Clemens Waechter

Gregor Keller

Alan L Renninger

Peter Grombach

James Shen

Thomas Hoffmann

Helmut Schneider

Gerhard Conzelmann

Heinz Pfizenmaier

Bernd Hofflinger

Thorsten Wierzkowski

Wolfgang Appel

Gayle W Miller, Jr

Tobias Florian

Clemens Wächter

A semiconductor having a n-doped cathode layer, a p-doped anode layer, and a drift region, arranged between the cathode layer and the anode layer, with a dopant concentration of at most 8&#xb7;10cm. The drift region has a lightly n-doped drift layer and a lightly p-doped drift layer, arranged between the n-doped drift layer and the anode layer, both drift layers each have a layer thickness of at least 5 &#x3bc;m. The cathode layer has a first section with a dopant concentration of at least 1&#xb7;10cmand a second section, arranged between the first section and the drift region, the second section has a layer thickness of at least 1 &#x3bc;m and a dopant concentration gradient that increases in the direction of the first section up to a dopant concentration maximum. The dopant concentration maximum is smaller or equal to the dopant concentration of the first section.

Stacked III-V semiconductor diode

A stacked III-V semiconductor diode comprising or consisting of GaAs, with a heavily n-doped cathode layer, a heavily p-doped anode layer, and a drift region arranged between the cathode layer and the anode layer with a dopant concentration of at most 8&#xb7;10cm, and a layer thickness of at least 10 &#x3bc;m, wherein the cathode layer has a delta layer section with a layer thickness of 0.1 &#x3bc;m to 2 &#x3bc;m and a dopant concentration of at least 1&#xb7;10cm.

A stacked III-V semiconductor diode comprising or consisting of GaAs with a highly n-doped cathode layer, a highly p-doped anode layer and a drift region arranged between the cathode layer and the anode layer, wherein the drift region has a low n-doped drift layer and a low p-doped drift layer, the n-doped drift layer is arranged between the p-doped drift layer and the cathode layer, both drift layers each have a layer thickness of at least 5 &#x3bc;m and, along the respective layer thickness, have a dopant concentration maximum of not more than 8&#xb7;10cm, the dopant concentration maxima of the two drift layers have a ratio of 0.1 to 10 to each other and a ratio of the layer thickness of the n-doped drift layer to the layer thickness of the p-doped drift layer is between 0.5 and 3.

A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

Stacked, high-blocking InGaAs semiconductor power diode

A stacked high-blocking III-V power semiconductor diode, with a p+ or n+ substrate layer, a p&#x2212; layer, an n&#x2212; region with a layer thickness of 10 &#x3bc;m-150 &#x3bc;m, and an n+ or p+ layer, wherein all layers comprise a GaAs compound, a first metallic contact layer and a second metallic contact layer and a hard mask layer with at least one seed opening, wherein the hard mask layer is integrally bonded to the substrate layer or integrally bonded to the p&#x2212; layer, the n&#x2212; region extends within the seed opening and over an edge region, adjacent to the seed opening, of a top side of the hard mask layer and the n&#x2212; region within the seed opening is integrally bonded to the p&#x2212; layer or to the n+ substrate layer and in the edge region of the top side of the hard mask layer to the hard mask layer.

Stacked high-blocking III-V power semiconductor diode

IGBT semiconductor structure having a psubstrate, an nlayer, at least one p region adjacent to the nlayer, and at least one nregion adjacent to the p region, a dielectric layer and three terminal contacts. The p region forms a first p-n junction together with the nlayer, and the nregion forms a second p-n junction together with the at least one p region. The dielectric layer covers the first p-n junction and the second p-n junction. The second terminal contact is implemented as a field plate on the dielectric layer and a doped intermediate layer with a layer thickness of 1 &#x3bc;m-50 &#x3bc;m and a dopant concentration of 10-10cmis arranged between the psubstrate and the nlayer, wherein the intermediate layer is integrally joined to at least the psubstrate.

GaAS based IGBT semiconductor structure

A stacked III-V semiconductor diode having an nlayer having a first surface, a second surface, a dopant concentration of 10N/cmto 10N/cmand a layer thickness of 50 &#x3bc;m to 1,000 &#x3bc;m, a player, which is integrally connected to the first surface and has a dopant concentration of 5&#xb7;10N/cmto 5&#xb7;10N/cm, an nlayer, which is integrally connected to the second surface and has a dopant concentration of at least 10N/cm. The player, the nlayer and the nlayer each having a monolithic design and each being made up of a GaAs compound. The dopant concentration of the nlayer having a first value on the first surface and a second value on the second surface, and the second value of the dopant concentration being greater than the first value at least by a factor between 1.5 and 2.5.

A stacked III-V semiconductor component having a pregion with a top side, a bottom side, and a dopant concentration of 5&#xb7;10-5&#xb7;10N/cm, a first nlayer with a top side and a bottom side, a dopant concentration of 10-10N/cm, and a layer thickness of 10-300 &#x3bc;m, an nregion with a top side, a bottom side, and a dopant concentration of at least 10N/cm, wherein the pregions, the nlayer, and the nregion follow one another in the stated order, are each formed monolithically, and each comprise a GaAs compound or consist of a GaAs compound, the nregion or the pregion is formed as the substrate layer, and the nlayer comprises chromium with a concentration of at least 10N/cmor at least 10N/cm.

Stacked III-V semiconductor component

A method and stacked semiconductor device having a top surface, a bottom surface, and at least one side surface that connects the top surface with the bottom surface. The bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer. On the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged. The first and second semiconductor layers are formed of a III-V material or consist of a III-V material. The first and second conductivity types are different. The top surface is at least partially formed by a passivation layer. Along the side surface, an amorphized and/or insulating region extending to a depth is formed, and the depth is perpendicular or substantially perpendicular to the layer stack.

Method for fabricating a semiconductor device and a semiconductor device

A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a pregion, an nlayer, and an nregion. The pregion, the nlayer, and the nregion follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The nregion or the pregion is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the nlayer or of an intermediate layer adjacent to the nlayer and to the pregion and the first and the second peripheral edges each have a width of at least 10 &#x3bc;m.

A stacked III-V semiconductor diode having an n-layer with a dopant concentration of at least 10N/cm, an n-layer with a dopant concentration of 10-10N/cm, a layer thickness of 10-300 microns, a p-layer with a dopant concentration of 5&#xd7;10-5&#xd7;10cm, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n-layer or the p-layer is formed as the substrate and a lower side of the n-layer is materially bonded with an upper side of the n-layer, and a doped intermediate layer is arranged between the n&#x2212;-layer and the p+-layer and materially bonded with an upper side and a lower side.

III-V semiconductor diode

A stacked III-V semiconductor diode that has an nlayer having a dopant concentration of at least 10N/cm, an nlayer having a dopant concentration of 10N/cmto 10N/cm, a layer thickness of 10 &#x3bc;m to 300 &#x3bc;m, a player having a dopant concentration of 5&#xb7;10N/cmto 5&#xb7;10cmand a layer thickness greater than 2 &#x3bc;m, the layers following each other in the specified order, each including a GaAs compound or being made from a GaAs compound and having a monolithic design, the nlayer or the player being a substrate, and a lower side of the nlayer being integrally connected to an upper side of the nlayer. The stacked III-V semiconductor diode including a first defect layer having a layer thickness greater than 0.5 &#x3bc;m, the defect layer being situated within the nlayer.

A stacked Schottky-diode having a stack with a top side and a bottom side. The stack has at least three semiconductor layers, and a first connection contact layer materially connected to the bottom side of the stack. A second connection contact layer is connected to the top side of the stack, wherein the second connection contact layer forms a Schottky contact. The second connection contact layer is disposed in a partial region of the top side and the second connection contact layer is bounded by edges. The first semiconductor layer, formed as an nlayer, is placed on the bottom side of the stack and the first semiconductor layer. A second semiconductor layer, formed as an nlayer, is placed on the first semiconductor layer. A third semiconductor layer formed as a player is placed on the second semiconductor layer.

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Brackenheim, Germany

Volker Dudek