Sambanova Systems, Inc.

Other

Siemens Aktiengesellschaft

Texas Instruments Corporation

Broadcom Corporation

Hitachi America, Ltd.

Alliacense Limited LLC

Vojin G Oklobdzija

Matthew M Kim

Aamir A Farooqui

Farzad Chehrazi

Rod G Fleck

Roger D Arnold

Richard G Yamasaki

Bruce Holmer

David K Chin

Eric John Chesters

Borivoje Nikolic

Leo Fu

Michael Leung

Wei-Jen Li

Andy W Yu

Vladimir Stojanovic

A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

System of free running oscillators for digital system clocking immune to process, voltage and temperature (PVT) variations

A floating-point accumulator circuit includes a floating-point input having an input significand field and a first shifter coupled to the input significand field and providing an output of the input significand field shifted by a first amount. A carry-save adder has a first, second, and third input and an output. The first input is coupled to the output of the first shifter and the output provides carry bits and sum bits representing a summation of the first input, the second input, and the third input as a significand of the accumulated value. Shifters are also coupled to the carry bits and the sum bits of the output of the carry-save adder to respectively provide the carry bits and the sum bits, both shifted by a second amount, to the second input and the third input of the carry-save adder.

Floating point accumulater with a single layer of shifters in the significand feedback

A floating-point accumulator circuit includes an addend input register having an addend exponent and an addend significand and an accumulation register with a first portion to hold a representation of an accumulation exponent and a second portion to hold a representation of an accumulation significand. A control circuit is also included to generate an accumulator zero control signal and an addend zero control signal based on the addend exponent and the accumulation exponent. It also includes an adder circuit with an output an input of the accumulation register. A first zeroing circuit sends either a zero or a value based on the addend significand to a first input of the adder circuit based on the addend zero control signal, and a second zeroing circuit sends either zeros or a value based on the accumulator significand to a second input of the adder circuit, based on the accumulator zero control signal.

Floating-point accumulator

A clocked storage element comprises a first latch having an input data node, a clock input node and a first latch output data node, and a second latch having an input connected to the first latch output data node, a clock input node and a second latch output data node. The first and second latches can have a clocked pull-up current path consisting of two p-channel transistors between their respective output data nodes and the VDD supply line, and a clocked pull-down current path consisting of two n-channel transistors between their respective output data nodes and the VSS supply line.

Fast clocked storage element

A Floating point Multiply-Add, Accumulate Unit, supporting BF16 format for Multiply-Accumulate operations, and FP32 Single-Precision Addition complying with the IEEE 754 Standard is described with exception handling. Operations including exception handling in a way that does not interfere with execution of data flow operations, overflow detection, zero detection and sign extension are adopted for 2's complement and Carry-Save format.

Floating point multiply-add, accumulate unit with exception processing

Floating point Multiply-Add, Accumulate Unit, supporting BF16 format for Multiply-Accumulate operations, and FP32 Single-Precision Addition complying with the IEEE 754 Standard. The Multiply-Accumulate unit uses higher radix and longer internal 2's complement significand representation to facilitate precision as well as comparison and operation with negative numbers. The addition is performed using Carry-Save format to avoid long carry propagation and speed up the operation. Operations including overflow detection, zero detection and sign extension are adopted for 2s complement and Carry-Save format. Handling of Overflow and Sign Extension allows for fast operation relatively independent on the size of the accumulator.

Floating point multiply-add, accumulate unit with carry-save accumulator

Floating point Multiply-Add, Accumulate Unit, supporting BF16 format for Multiply-Accumulate operations, and FP32 Single-Precision Addition complying with the IEEE 754 Standard. The Multiply-Accumulate unit uses higher radix and longer internal 2's complement significand representation to facilitate precision as well as comparison and operation with negative numbers. The addition can be performed using Carry-Save format to avoid long carry propagation and speed up the operation. The circuit uses early exponent comparison to shorten the accumulate pipeline stage. Operations including overflow detection, zero detection and sign extension are adopted for 2s complement and Carry-Save format.

Floating point multiply-add, accumulate unit with combined alignment circuits

System of free running oscillators for digital system clocking immune to process, voltage, and temperature (PVT) variations

Methods and apparatus for an encryption processor for performing accelerated computations to establish secure network sessions. The encryption processor includes an execution unit and a decode unit. The execution unit is configured to execute Montgomery operations and including at least one adder and at least two multipliers. The decode unit is configured to determine if a square operation or a product operation needs to be performed and to issue the appropriate instructions so that certain multiply and/or addition operations are performed in parallel in the execution unit while performing either the Montgomery square or Montgomery product operation.

Encryption processor for performing accelerated computations to establish secure network sessions connections

Reduction of the complexity of a Viterbi-type sequence detector is disclosed. It was based on elimination of less probably taken branches in the trellis. The method is applied to the design of the E PR4 channel with 8/9 rate sliding block trellis code. Coding, by itself eliminates two states by coding constraints, and the disclosed method reduces the number of required ACS units from 14 to 11, while reducing their complexity as well. For the implementation of E PR4 detection, 4 4-way, 3 3-way, 3 2-way and one 1-way ACSs are needed. System simulations show no BER performance drop at common SNRs when compared with a full 16-state E PR4 implementation in magnetic disk drives.

Reduced-complexity sequence detection

A partitioned multiplier circuit which is designed for high speed operations. The multiplier of the present invention can perform one 32&times;32 bit multiplication, two 16&times;16 bit multiplications (simultaneously) or four 8&times;8 bit multiplications (simultaneously) depending on input partitioning signals. The time required to perform either the 32&times;32 bit or the 16&times;16 bit or the 8&times;8 bit multiplications is constant. Therefore, multiplication results are available with a constant latency regardless of operand bit-size. In one embodiment, the latency is two clock cycles but the multiplier circuit has a throughput of one clock cycle due to pipelining. The input operands can be signed or unsigned. The hardware is partitioned without any significant increase in the delay or area and the multiplier can provide six different modes of operation. In one embodiment, Booth encoding is used for the generation of 17 partial products which are compressed using a compression tree into two 64-bit values. This is performed in the first pipeline stage to generate a sum and a carry vector. These values are then added, in the second pipestage, using a carry propagate adder circuit to provide a single 64-bit result. In the case of 16&times;16 bit multiplication, the 64-bit result contains two 32-bit results. In the case of 8&times;8 bit multiplication, the 64-bit result contains four 16-bit results. Due to its high operating speed, the multiplier circuit is advantageous for use in multi-media applications, such as audio/visual rendering and playback.

High performance universal multiplier circuit

An improved Booth encoder/selector circuit having an optimized critical path. The Booth encoder has a number of inverters coupled to several of the input multiplier bits. The inverted/non-inverted multiplier bits are then fed as inputs to NAND gates as well as a series of pass gates. The outputs of the pass gates are then fed as inputs to other NAND gates. The output from the NAND gates serve as control signals for controlling the Booth selector. The Booth selector is comprised of inverters and pass gates. Multiplicand bits are input to the pass gates. The control signals generated by the Booth encoder are selectively coupled to the inverters and pass gates such that they control which one of a plurality of multiplicand bits are selected for output. Basically, the Booth selector functions as a multiplexer whereby one of the following is output: the multiplicand bit is multiplied by zero, multiplied by one, multiplied by negative one, multiplied by two, or multiplied by negative two. The Booth encoder/selector is used in a multiplier circuit to minimize the number of partial products. An adder is then used to sum all of the partial products to arrive at the final answer. In the present invention, the critical path has been optimized such that the overall speed of the multiplier is greatly improved.

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Berkeley, CA, United States of America

Vojin G Oklobdzija