Hewlett-Packard Company

Other

Voddarahalli K Nagesh

Jacques Leibovitz

Daniel J Miller

Kim Hong Chen

Jeffrey G Hargis

Peter F Dawson, Deceased

Peter F Dawson

Robert A Schuchard

Richard L Wheeler

Clinton C Chao

Cheng-Cheng Chang

Maria L Cobarruviaz

John P Scalia

Greg M Irby

Hilmar W Spieth

Howard H Nakano

Bahram Afshari

By Shirley Dawson, Executor

A silicon die, such as an integrated circuit, is reworkably bonded to a copper heat spreader. The silicon-copper bond exhibits high compliance under conditions of thermal stress even though there is a significant thermal coefficient of expansion difference between silicon and copper. A compliant adhesive is applied to the surface of one of the silicon die and the copper heat spreader and is cured. Thereafter, a thermoplastic adhesive is applied to bond the silicon die to the copper heat spreader. A composite bond is thereby produced, including a highly compliant layer and a thermoplastic layer. The die may be reworked by heating the thermoplastic adhesive until the bond begins to soften and the die is released.

Reworkable die attachment to heat spreader

The flip chip package described is comprised of a substrate, a ring structure attached to the substrate, a heat removal structure, and a chip thermally coupled to the heat removal structure. The package lid is comprised of a ring structure and a heat removal structure. The ring structure and heat removal structure are separated until after attachment of the ring structure to the substrate allowing the ring structure to be brazed to the substrate. Brazing the ring structure to the substrate decreases the mechanical stress to the chip. A die attach material, between the first major surface of the die and the first major surface of the heat removal structure, adheres the die to and thermally couples the die to the heat removal structure. The die attach layer is of a predetermined thickness and thus provides a determined low thermal resistance making the thermal performance of the package certain.

Low cost, high thermal performance package for flip chips with low

A flip-chip IC package (10) provides a thermally-conductive lid (20) attached to a backside of the chip (12) by a die attach layer (18) of a predetermined thickness range. A rim (22), preferably KOVAR iron-nickel alloy, is formed on the lid (20) with a depth (44) less than a sum (42) of a thickness of the chip, the interconnects (16), and a minimum final thickness (40) of the die attach layer (18) by a predetermined margin (46). An initial thickness of thermally-filled epoxy is applied to the backside of the chip and a layer of lid attach epoxy (24) is applied to the rim of the lid in a thickness sufficient to span the predetermined margin. The lid is floated on the die attach layer (18) with the rim of the lid surrounding the chip and floating on the lid attach material. The lid is clamped against the chip with a force sufficient to compress the die attach material to a predetermined thickness in a range less than the initial thickness and not less than the minimum final thickness (40). An oxide layer, such as an iron or iron-alloy oxide layer, is formed on the bottom surface of the rim. A spacer is placed on the backside of the chip within the die attach material (18), to define the minimum final thickness (40) of the die attach layer. A beveled or stepped vent hole is formed in the lid and plugged and sealed.

Reliable low thermal resistance package for high power flip clip ICs

The present invention is a double headed pin for electrically interconnecting a PGA substrate carrier to a surface mount printed circuit board. The double headed pins provide for a stronger interconnection to the conductive pads on the surface mount printed circuit board. The increase in contact and soldering wetting area makes the interconnections stronger and more durable.

Surface mounting pin grid arrays

A composite transversely plastic interconnect for a microcarrier produces a carrier-to-substrate bond having low electrical resistance and high mechanical strength, significant bond height to mediate TCE mismatch between dissimilar carrier and substrate materials, and sufficient gap between the carrier and the substrate to permit effective post solder cleaning of the interconnect. A contact array consisting of solder balls is placed directly onto either of a carrier or a substrate interconnect surface with a stencil positioned to the chosen interconnect surface. The solder balls may have a selected melting temperature. Additionally, the solder balls may have a metallic coating, such as nickel or copper, or molten solder. The carrier and substrate are joined by mating an interconnect surface of each and applying heat. Solder paste may be applied to one of the interconnect surfaces to add additional height to the joint and compensate for lack of coplanarity between the carrier and the substrate.

Composite transversely plastic interconnect for microchip carrier

An integrated circuit is reworkably attached to a circuit board in a manner that forms a compliant bond which is stable under conditions of high thermal stress and thermal coefficient of expansion mismatch. A thermoplastic adhesive having a melting temperature higher than integrated circuit operating temperature is coated on the integrated circuit and dried. The adhesive is then cured. The coated integrated circuit is bonded to the circuit board with a thermosetting epoxy having a low curing temperature, such that curing the adhesive does not damage the circuit board. The integrated circuit is readily removed from the circuit board without damaging the board by heating the integrated circuit to soften the bond between the integrated circuit and the circuit board at the thermoplastic adhesive interface. An alternate embodiment of the invention provides a copper plate interface that is soldered to the circuit board, and to which an integrated circuit is permanently bonded. Reworkability is achieved by flowing the solder bond and removing the copper plate/integrated circuit assembly.

Reworkable die attachment

A specialized etching method for producing fine-geometry gold circuit structures. Production thereof is accomplished by maintaining a constant gold etching rate. Metal etching normally slows as the amount of dissolved gold (a reaction product of the etching process) increases. To remove the dissolved gold, one method involves cooling the etchant to precipitate a gold complex therefrom. The remaining, recovered etchant is then heated and made available for continued etching. Another method involves a cathode/anode assembly which is immersed in the etchant. Activation of the assembly recovers metallic gold and regenerates the etchant. These methods, when used continuously or periodically in a dip or spray etching system, maintain a constant etching rate. As a result, fine-geometry circuit structures may be accurately produced while minimizing material costs (e.g. etchant use) and minimizing the production of undesirable waste products and disposal expenses associated therewith.

Controlled etching process for forming fine-geometry circuit lines on a

A multi-chip module is configured using an aluminum nitride, or AlN, multi-chip substrate, sandwiched chip side down under an extruded aluminum convection cooled heat sink. An alignment ring includes grooves for control of z-axis elastomeric conductors slightly compressed between the chip connection surface of the substrate and the top surface of a PCB to provide the interconnections therebetween. The alignment ring includes a stopper portion which controls the height of the heat sink above the PCB as well as a smaller rail portion which controls the height of the substrate above the PCB. The good thermal conductivity, ruggedness and relatively good TCE match of the AlN substrate to the silicon chips permits a convenient, dense and thermally rugged MCM.

Aluminum nitride multi-chip module

An electronic component assembly and method for enhancing density and operational speed. The assembly includes a plurality of integrated circuit chips which are mounted to a planar surface of a substrate, preferably a printed circuit board, with the opposed major faces of the chips being perpendicular to the planar surface. One of the major faces of each chip is the active face having a pattern of signal pads. The pads are disposed along the face periphery adjacent to the edge of the chip contacting the printed circuit board. The signal pads have solder bumps which can be soldered directly to contact pads on the printed circuit board. A passivating edge-coating on each chip protects the chip and prevents electrical shorting on the printed circuit board. A source of fluid directs a cooling flow along the large area major surfaces of the chips.

Growing community of inventors

Cupertino, CA, United States of America

Voddarahalli K Nagesh