National Semiconductor Corporation

Eastman-kodak Company

Texas Instruments Corporation

Other

Maxim Integrated Products, Inc.

Vladislav Vashchenko

Peter J Hopper

Philipp Lindorfer

Yuri Mirgorodski

Ann Margaret Concannon

Marcel A Ter Beek

Andy Strachan

Peter B Johnson

Robert Drury

William David French

Vladimir Kuznetsov

Alexei Sadovnikov

Michael Mian

Andrew Derek Strachan

Richard Wendell Foote, Jr

Antonio Gallerano

Trevor Niblock

Iouri N Mirgorodski

Pascale Francis

Manuel Carneiro

Marcel Ter Beek

Punit Bhola

Konstantin G Korablev

Pavel Poplevine

James Paul Di Sarro

Kyuwoon Hwang

Hon Kin Chiu

Prasad Chaparala

Augusto Tazzoli

Erika Lynn Mazotti

Willem J Kindt

Douglas Robert Farrenkopf

Douglas Brisbin

Alexander Burinskiy

Lawrence Richard Skrenes

David Tsuei

Douglas Stuart Smith

Philip Lindorpher

Yuri Mirgorodsky

Peter J Hoppet

Wendy Greig

Andy Strachon

Sudhir Mulpuru

Marcel Ter Book

Alexel Sadovnikov

Silicon-controlled rectifier (SCR) based circuit for ECG protection under defibrillator pulse is disclosed. The SCR-based clamp is a symmetric structure for dual-direction voltage tolerance protection based on two anti-series P-well/N-well lateral blocking junctions isolated from P-substrate by the N-buried layer. The injector regions (n+/p+) are substantially lengthened in order to accommodate a larger number of contact rows than typically used for ESD pulses specification. A stack of metal layers may also be used to provide high current and heat-sink capability with each electrode metal layer fully filled with VIAs.

Integrated defibrillation pulse protector

In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.

ESD clamp with auto biasing under high injection conditions

A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.

DMOS transistor with a slanted super junction drift structure

In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.

Ultra high voltage GaN ESD protection device

In an extended drain MOS device used in high voltage applications, switching characteristics are improved by providing for at least one base contact in the active region in the extended drain space.

High voltage MOS array with gate contact on extended drain region

In an SCR ESD protection circuit, the n-type emitter of the SCR is controlled to receive electron current only during an ESD event, thereby defining PNP characteristics during normal operation and SCR characteristics during an ESD event.

In the case of adjacent high voltage nodes in which one node is protected by a lateral BJT clamp, the irreversible burnout due to transient latch-up between the two adjacent high voltage pins of the structure is avoided by increasing the base contact region by including a sinker connected to the base.

High holding voltage BJT clamp with embedded reverse path protection in BCD process

A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.

DMOS Transistor with a cavity that lies below the drift region

In an LVTSCR, an avalanche diode based control circuit controls both the base of the internal PNP of the LVTSCR as well as the gate of the LVTSCR.

High voltage tolerant SCR clamp with avalanche diode triggering circuit

A high voltage ESD protection diode wherein the p-n junction is defined by a p-well and an n-well and includes a RESURF region, the diode including a field oxide layer formed on top of the p-well and n-well, wherein the parameters of the diode are adjustable by controlling one or more of the junction width, the length of the RESURF region, or the length of the field oxide layer.

EDS protection diode with pwell-nwell resurf

In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.

Low triggering voltage DIAC structure

In an active clamp implemented in a 5V complementary BiCMOS process, the footprint of the active clamp, which includes at least one NMOS clamp stack, is reduced by introducing a BJT into the circuit to allow the number of NMOS clamp stacks to be reduced.

High voltage tolerant, small footprint BJT-CMOS active clamp

In a gated diode ESD protection structure, the gate is split into two parts to divide the total reverse voltage between two gate regions.

Split-gate ESD diodes with elevated voltage tolerance

A circuit includes multiple doped regions in a substrate. A first of the doped regions has a tip proximate to a second of the doped regions and is separated from the second doped region by an intrinsic region to form a P-I-N structure. The circuit also includes first and second electrodes electrically coupled to the first and second doped regions, respectively. The electrodes are configured to supply voltages to the first and second doped regions to reverse bias the P-I-N structure and generate light. The first doped region could include multiple tips, the second doped region could include multiple tips, and each tip of the first doped region could be proximate to one of the tips of the second doped region to form multiple P-I-N structures. The P-I-N structure could also be configured to operate in double avalanche injection conductivity mode with internal positive feedback.

High-speed avalanche light emitting diode (ALED) and related apparatus and method

Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.

Galvanic isolation that incorporates a transformer with an optical link and that can be integrated onto a single semiconductor substrate

Growing community of inventors

Palo Alto, CA, United States of America

Vladislav Vashchenko