Intel Corporation

Other

Motorola Corporation

Net Navigation Systems, LLC

Vladislav Kopzon

Alexander Sgouros

Noam Halevy

Eliezer Tamir

Ben-Zion Friedman

Eliel Louzoun

Reuven Rozic

Tsvika Kurts

Moti Kurnick

Itai Katz

Yaniv Hayat

Noam Halevi

Gilad Shayevitz

A system can include a host machine connected to a device under test (DUT) by a serial link. The host machine can include a serial interface, such as a Thunderbolt interface, and a memory. The DUT can include a trace data source, a high-speed trace interface (HTI) to receive trace data from the trace data source, a serial interface (such as a Thunderbolt interface), and a PIPE interface connecting the HTI with the serial interface. The HTI is to send the trace data to the serial interface through the PIPE interface. The serial interface is to packetize the trace data into a conforming packet format, and send the trace data as a packet across the serial link to the host machine. The host machine can receive the trace data at the host-side serial interface, store the trace data in memory, and process the trace data for debugging the DUT.

Closed chassis debugging through tunneling

Systems, devices, computer program products, and methods include determining by a connection manager that a connected device can be enhanced by an asymmetrical multi-lane link. The connection manager can use system parameters, including bandwidth information, to switch a direction of one or more lanes of the multi-lane link. The connection manager can use register setting instructions to change register settings on the host side and on the device side to switch the direction of one or more lanes of the multi-lane link.

Systems, methods, and devices for dynamic high speed lane direction switching for asymmetrical interfaces

A method and apparatus to reduce memory required in a network interface controller to store per flow state information associated with a network connection is provided. Instead of storing per flow state information for a connection in the network interface controller at an endpoint of the connection, the per flow state information for the connection is stored in memory external to the network interface controller. The stored state information is conveyed in a packet by the network interface controller between the endpoints of the connection. For a Transmission Control Protocol (TCP) connection, the state information is conveyed between the endpoints of the TCP connection in a TCP option included in the TCP header in the packet.

Method and apparatus to manage per flow state

A system and method are provided for prioritizing network processor information flow in a channel service manager (CSM). The method receives a plurality of information streams on a plurality of input channels, and selectively links input channels to CSM channels. The information streams are stored, and the stored the information streams are mapped to a processor queue in a group of processor queues. Information streams are supplied from the group of processor queues to a network processor in an order responsive to a ranking of the processor queues inside the group. More explicitly, selectively linking input channels to CSM channels includes creating a fixed linkage between each input port and an arbiter in a group of arbiters, and scheduling information streams in response to the ranking of the arbiter inside the group. Finally, a CSM channel is selected for each information stream scheduled by an arbiter.

Channel service manager

Channel service manager with priority queuing

A multi-master bus system (,) comprises bus (,), a plurality of bus devices (,), coupled to the bus, including masters (,), and slaves (,), a memory controller (,) for controlling the data exchange on bus (,), having a memory (,) for storing a transaction type value with respect to each slave (,). The multi-master bus system (,) comprises further an arbiter (,) for performing bus arbitration, arbiter (,) having logic for conditionally subsequently granting the bus (,) to a master of an initiating transaction for a closing transaction depending on the transaction type value of the slave of the initiating transaction. The multi-master bus system makes atomic or indivisible transactions possible on a bus without changing the bus width or the bus protocol.

Multi-master bus system performing atomic transactions and method of operating same

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Haifa, Israel

Vladislav Kopzon