Analog Devices,inc.

Synopsys, Inc.

Intel Corporation

Vladimir Zlatkovic

Eric G Nestler

Jeffrey Venuti

Jeffrey G Bernstein

David C Reynolds

Benjamin Vigoda

Alexander Alexeyev

William Bradley

Kartik Nanda

David Da-Wei Lin

Kuan Zhou

Yamin Du

Alex Alexeyev

De Zhong Cheng

Xiao Yun

Alexander A Alexeyev

Abdelrahman Alaa Gouda

Youssef Mamdouh El-Toukhy

Shefali Walia

An apparatus for processing an input signal from a memory includes an attenuator circuit and an analog front end (AFE) circuit. The attenuator circuit attenuates the input signal from the memory to produce an attenuated signal. The AFE circuit includes a first amplification stage and a second amplification stage. The first amplification stage has an n-type metal-oxide semiconductor (NMOS) transistor. The NMOS transistor has a gate that receives the attenuated signal from the attenuator circuit. The second amplification stage has a p-type metal-oxide semiconductor (PMOS) transistor. The PMOS transistor has a gate that receives the attenuated signal from the attenuator circuit. Outputs of the first amplification stage and the second amplification stage are electrically coupled to a common output of the AFE circuit.

Multi-protocol analog front end circuit

An output driver includes a pullup driver, a pulldown driver and a resistive element. The pullup driver includes a first PMOS transistor having a source coupled to a first supply voltage and a gate receiving a first data representative of a transmitted data, and a second PMOS transistor having a source coupled to a drain of the first PMOS transistor and a gate receiving a first analog signal. The pulldown driver includes a first NMOS transistor having a source coupled to a second supply voltage and a gate receiving a second data representative of the transmitted data, and a second NMOS transistor having a source coupled to a drain of the first NMOS transistor, a drain coupled to a drain of the second PMOS transistor, and a gate receiving a second analog signal. The resistive element is coupled between the drain terminal of the second NMOS transistor and a pad.

Configurable, high speed and high voltage tolerant output driver

Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.

Duty cycle adjustment circuit with independent range and step size control

An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Charge sharing time domain filter

In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Charge sharing analog computation circuitry and applications

Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.

Analog computation

A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Storage devices with soft processing

A voltage regulator comprising two feedback loops for regulating a load voltage, where the first feedback loop comprises a pass transistor to source current to the load, and the second feedback loop comprises a shunt transistor to shunt current from the pass transistor to ground. The use of two feedback loops allows the design of a voltage regulator in which it small-signal impedance, as seen by a power rail, has a phase not less than &#x2212;90 degrees. This mitigates interactions between the power rail and the voltage regulator that may lead to oscillations, without the need for a relatively large de-coupling capacitor. Other embodiments are described and claimed.

Growing community of inventors

Belmont, MA, United States of America

Vladimir Zlatkovic