Memc Electronic Materials, Inc.

Globalwafers Co., Ltd.

Sunedison Semiconductor Limited (uen201334164h)

Sunedison, Inc.

Sunedison Semiconductor Limited

Memc Singapore Pte. Ltd. (uen200614794d)

Sunedison Semiconductor Ltd. (uen201334164h)

Vladimir V Voronkov

Robert J Falster

John Allen Pitney

Peter D Albrecht

Paolo Mutti

Gabriella Borionetti

Francesco Bonoli

Mohsen Banan

Massimiliano Olmo

Daniela Gambaro

Marco Cornara

Maria Porrini

Roberto Scala

Paolo Collareta

Maria Giovanna Pretto

Galina I Voronkova

Anna V Batunina

Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Apparatus for stressing semiconductor substrates

A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.

Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method

Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Processes and apparatus for preparing heterostructures with reduced strain by radial compression

Processes and apparatus for preparing heterostructures with reduced strain by radial distension

Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.

Silicon wafers with suppressed minority carrier lifetime degradation

Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400&#xb0; C. and about 600&#xb0; C. for at least about 1 hour.

Production of high precipitate density wafers by activation of inactive oxygen precipitate nuclei

Processes for suppressing minority carrier lifetime degradation in silicon wafers

A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.

Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering

The present invention generally relates to a high resistivity CZ silicon wafer, or a high resistivity silicon structure derived therefrom, and a process for the preparation thereof. In particular, the high resistivity silicon structure comprises a large diameter CZ silicon wafer as the substrate thereof, wherein the resistivity of the substrate wafer is decoupled from the concentration of acceptor atoms (e.g., boron) therein, the resistivity of the substrate being substantially greater than the resistivity as calculated based on the concentration of said acceptor atoms therein.

High resistivity silicon structure and a process for the preparation thereof

A process for the preparation of low resistivity arsensic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.

A process for producing a single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.

Growing community of inventors

Merano, Italy

Vladimir V Voronkov