Texas Instruments Corporation

Dcg Systems Gmbh

Fei Efa, Inc.

Fei Comapny

Vladimir Ukraintsev

Mike Berkmyre

John M Sanders

Richard Stallcup

Sergiy Pryadkin

Duncan M Rogers

Thomas Dyer Bonifield

Ronen Benzion

Israel Niv

Craig Lawrence Hall

System for performing in-line nanoprobing on semiconductor wafer. A wafer support or vertical wafer positioner is attached to a wafer stage. An SEM column, an optical microscope and a plurality of nanoprobe positioners are all attached to the ceiling. The nanoprobe positioners have one nanoprobe configured for physically contacting selected points on the wafer. A force (or touch) sensor measures contact force applied by the probe to the wafer (or the moment) when the probe physically contacts the wafer. A plurality of drift sensors are provided for calculating probe vs. wafer alignment drift in real-time during measurements.

Through process flow intra-chip and inter-chip electrical analysis and process control using in-line nanoprobing

Apparatus for electrical and optical nanoprobing at resolution beyond optical diffraction limit. Navigation microscope is configured for navigation to a region of interest. A probe spatial positioner supports a fork and an oscillating piezotube is attached to the free end of the fork and provides an output indicating of a distance to the sample. A single-mode optical fiber having a near-field transducer formed at an end thereof is attached to the oscillating piezotube such that the near-field transducer extends below the oscillating piezotube towards the sample. A photodetector is positioned to detect photons collected from the sample. The near-field transducer may be formed as a tapered section formed at the end of the single-mode optical fiber, a metallic coating formed at a tip of the tapered section, and an aperture formed in the metallic coating so as to expose the tip of the tapered section through the metallic coating.

Optical nanoprobing of integrated circuits

A method for testing an integrated circuit (IC) using a nanoprobe, by using a scanning electron microscope (SEM) to register the nanoprobe to an identified feature on the IC; navigating the nanoprobe to a region of interest; scanning the nanoprobe over the surface of the IC while reading data from the nanoprobe; when the data from the nanoprobe indicates that the nanoprobe traverse a feature of interest, decelerating the scanning speed of the nanoprobe and performing testing of the IC. The scanning can be done at a prescribed nanoprobe tip force, and during the step of decelerating the scanning speed, the method further includes increasing the nanoprobe tip force.

Probe-based data collection system with adaptive mode of probing controlled by local sample properties

A system for performing sample probing. The system including an topography microscope configured to receive three-dimensional coordinates for a sample based on at least three fiducial marks; receive the sample mounted in a holder; and navigate to at least a location on the sample based on the at least three fiducial marks and the three-dimensional coordinates.

System and method for non-contact microscopy for three-dimensional pre-characterization of a sample for fast and non-destructive on sample navigation during nanoprobing

A method comprising characterizing the dimensions of structures on a semiconductor device having dimensions less than approximately 100 nanometers (nm) using one of scanning probe microscopy (SPM) or profilometry.

Characterizing dimensions of structures via scanning probe microscopy

A system for analyzing a sample is described. The system for analyzing a sample includes a probe and a controller circuit. The controller circuit configured to control a movement of the probe to at least a first position and a second position on the sample based on navigation data. In response to the movement of the probe, the controller circuit is configured to adjust a force of the probe on the sample at the first position from a first force value to a second force value and the force of the probe on the sample from a third force value to a fourth force value at said second position on the sample. And, the controller circuit is configured to acquire sample data with the probe at the first position on the sample.

Probe-based data collection system with adaptive mode of probing

Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates with recessed regions for Si&#x2014;Ge epitaxial layers, is not cost effective for the commonly used metrology techniques: SEM, TEM and AFM. Scatterometry is technically unfeasible due to the number of elements and optical constants. The instant invention is a simplified scatterometry structure which reproduces the profiles of a structure to be profiled in a simpler structure that is compatible with conventional scatterometric techniques. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed.

Simple scatterometry structure for Si recess etch control

Provided is a method for manufacturing a semiconductor device. The method, in one embodiment, includes calibrating an inspection tool configured to obtain a measurement of a semiconductor feature, including: 1) providing a test structure comprising a substrate having a trench therein, and a post feature located over the substrate adjacent the trench. The post feature, in this embodiment, includes a second layer positioned over a first layer, wherein the first layer has a notch or bulge in a sidewall thereof; 2) finding a location of the notch or bulge relative to a different known point of the test structure using a probe of the inspection tool; and 3) calculating a dimension of the probe using the relative locations of the notch or bulge and the different known point.

Method for calibrating an inspection tool

A system () for characterizing surfaces can include a nanotip microscope () in a first pressure envelope () at a first pressure with an electrically conductive nanotip () mounted thereon for characterizing a sample surface. The system can also include an ion imaging system () within a second pressure envelope () at a second pressure. The second pressure can less than or equal to the first pressure and the pressure envelopes () can be separated by a pressure limiting aperture (PLA) (). The system can further include gas sources () for introducing into the first pressure envelope () at least one gas, and a voltage supply () coupled to the nanotip () for generating an electric field between the nanotip () and the PLA (). In the system, the electric field repels and ionizes molecules or atoms of the gas in proximity to the nanotip () and the ion imaging system () collects at least a portion the repelled and ionized molecules or atoms traversing the PLA () to image the nanotip ().

Nanotip repair and characterization using field ion microscopy

Measuring surface profiles of structures on integrated circuits is difficult when feature sizes are less than 100 nanometers. Atomic force microscopy provides surface profile measurement capability on flat horizontal surfaces, but has difficulty with three-dimensional structures such as MOS transistor gates, contact and via holes, interconnect trenches and photoresist patterns. An atomic force microscopy probe with two atomically sharp tips configured to facilitate measurements of three-dimensional structures is disclosed. A method of making such measurements using the disclosed probe and a method of fabricating an IC encompassing the method are also claimed.

Rocking Y-shaped probe for critical dimension atomic force microscopy

The present invention describes a plurality of scatterometry test structures for use in process control during fabrication of a semiconductor wafer having multilevel integrated circuit chips, many of said levels having a feature size of a critical dimension. The scatterometry test structures on the wafer are at each level, suitable to measure critical dimensions. The second level and each subsequent level of the test structures are located to fit into the same footprint area as the first level.

Growing community of inventors

Allen, TX, United States of America

Vladimir Ukraintsev