Agere Systems Inc.

Lsi Corporation

Lucent Technologies Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Agere Systems Guardian Corp.

Vladimir Sindalovsky

Lane Allen Smith

Mohammad Shafiul Mobin

Christopher John Abel

Gregory W Sheets

Craig B Ziemer

Joseph Anidjar

Ronald Lamar Freyman

Frederick Harrison Fischer

Donald Raymond Laturell

Pervez Mirza Aziz

Amaresh Virupanagouda Malipatil

Scott A Segan

Brett D Hardy

Parag Parikh

Ye Liu

Xingdong Dai

Peter C Metz

Mark Trafford

Jung Ho Cho

Jonathan Herman Fischer

William Burdett Wilson

Bahram Ghaffarzadeh Kermani

Jalil Fadavi-Ardekani

Steven E Strauss

Shawn Michael Logan

Max Jay Olsen

Kenneth Daniel Fitch

Yasser Ahmed

Jeffrey S Kueng

Sunil Srinivasa

Gary Schiessler

Srinivasa Gutta

Eric P Wilcox

Abhishek Duggal

Thomas F Gibbons, Jr

Philip N Jenkins

Niall Fitzgerald

Ravikumar K Charath

Robert M Kylor

James W Hofmann

Gary E Schiessler

Methods and apparatus are provided for adapting transmitter equalization coefficients based on receiver gain adaptation. Equalization coefficients of a transmitter that communicates over a channel with a receiver are adapted by determining if a gain value for an amplifier in the receiver is within a limit of the amplifier; and preventing one or more adjustments to the transmitter equalization coefficients if the gain value does not satisfy the upper or lower limit of the amplifier. The gain adjustments comprise, for example, up and down requests for the transmitter equalization coefficients. One or more enable flags can optionally be set based on whether the gain value is within the limit of the amplifier.

Methods and apparatus for adapting transmitter equalization coefficients based on receiver gain adaptation

Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer '0' and '1' discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Slicer trim methodolgy and device

Described embodiments provide for, in a receiver circuit, an adaptation process that adjusts the IQ-skew automatically to obtain proper eye centering in a data eye, thereby maximizing horizontal margin of the eye. The IQ-skew adaptation algorithm is realized with a 'biased' bang-bang phase detector (BBPD) oof a clock and data recovery circuit (CDR) that biases the weights applied to UP and DOWN outputs of the phase detector, rather than treating them equally. By weighting the BBPD UPs and DOWNs differently, the system locks to the left and right inner corners, and thereby is able to locate the center of the inner eye.

IQ-skew adaptation for a symmetric eye in a SerDes receiver

In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time decision feedback equalization (DFE) is employed.

Pattern-based loss of signal detector

A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

SerDes data sampling gear shifter

Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.

Joint transmitter and receiver gain optimization for high-speed serial data systems

In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels.

Alignment for multiple FIFO pointers

An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Loss of lock detector for clock and data recovery system

In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.

Serializer-deserializer clock and data recovery gain adjustment

In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.

CDR with digitally controlled lock to reference

In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Receiver training with cycle slip detection and correction

In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Pattern detector for serializer-deserializer adaptation

Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Methods and apparatus for pseudo asynchronous testing of receive path in serializer/deserializer devices

In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.

CDR with sigma-delta noise-shaped control

Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.

Methods and apparatus for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns

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Perkasie, PA, United States of America

Vladimir Sindalovsky